scholarly journals Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 476 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Shupeng Chen ◽  
Wei Li ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Source Region ◽  
Ultra Low Power ◽  
Narrow Bandgap ◽  
Order Of Magnitude ◽  
Drain Region ◽  
Aided Design

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

Microsensors for physical signals: Principles, device design, and fabrication technologies

1996 ◽  
Vol 74 (S1) ◽  
pp. 115-130 ◽  
Author(s):  
Arokia Nathan
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Electrical Signal ◽  
Single Chip ◽  
Research Activity ◽  
Rapid Pace ◽  
Silicon Based ◽  
Aided Design ◽  
New Generation ◽  
Physical And Chemical

Microsensors are miniaturized devices, fabricated using silicon-based and related technologies, that convert input physical and chemical signals into an output electrical signal. The key driving force in microsensor research has been the integrated circuit (IC) and micromachining technologies. The latter, in particular, is fueling tremendous activity in micro-electromechanical systems (MEMS). In terms of technology and design tools, MEMS is at a stage where microelectronics was 30 years ago and is expected to evolve at an equally rapid pace. The synergy between the IC, micromachining, and integrated photonics technologies can potentially spawn a new generation of microsystems that will feature a unique marriage of microsensor, signal-conditioning and -processing circuitry, micromechanics, and optomechanics possibly on a single chip. In this paper, the physical transduction principles, materials considerations, process-fabrication technologies, and computer-aided-design (CAD) tools will be reviewed along with pertinent examples drawn from our microsensor research activity at the Microelectronics Laboratory, University of Waterloo.

Up Close: The Interuniversity Microelectronics Center (IMEC), Leuven, Belgium

MRS Bulletin ◽  
1989 ◽  
Vol 14 (6) ◽  
pp. 35-38 ◽  
Author(s):  
Dirk Denoyelle
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Systems Design ◽  
System Level ◽  
Clean Room ◽  
Integrated Circuit Design ◽  
Processing Technologies ◽  
Wide Range ◽  
Application Specific Integrated Circuit ◽  
Aided Design

The Interuniversity Microelectronics Center, Leuven, Belgium (IMEC) is one of the world's largest independent research centers for microelectronics. It was established in 1984 by the Flemish government as a part of a comprehensive program to promote high technology in Flanders, Belgium. Benefiting from existing experience available mainly at the University of Leuven, IMEC moved into its present facilities in 1986 (Figure 1).The Center covers a wide range of research topics in the microelectronics domain—VLSI systems design methodologies, advanced semiconductor processing, materials, packaging, and more.About 50 people work on computer-aided design, developing a series of “true” silicon compilers: CATHEDRAL. With this software, ASIC (application specific integrated circuit) design becomes extremely attractive, since CATHEDRAL covers design from the high system level down to layout.INVOMEC, the training division of IMEC, supports universities in ASIC design. It trains people for both educational institutes and industry in chip design, makes available the necessary software, and has a well-established Multi Project Chip—Multi Project Wafer service.The Processing Technologies and Materials Divisions involve about 200 people and have a 3,600 m2 clean room at their disposal. The clean room consists of a 20% class 10 area with a fast-turnaround prototyping line and an 80% class 1000 area.IMEC's objectives are: to perform research in the microelectronics field, supporting both industry and universities, and to stimulate the microelectronics industry in Flanders.IMEC performs research on both silicon and III-V technologies.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

scholarly journals TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

Coatings ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 278 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Shulong Wang ◽  
Haiwu Xie
Keyword(s):  
Integrated Circuits ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Source Region ◽  
Cutoff Frequency ◽  
Tunneling Current ◽  
Frequency Characteristics ◽  
Device Structure ◽  
Ultra Low Power ◽  
Current Switching

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

scholarly journals Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 887
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Circuit Simulation ◽  
Electrical Coupling ◽  
Ring Oscillator ◽  
Model Parameters ◽  
Flip Flop ◽  
Circuit Simulator ◽  
Aided Design ◽  
Better Than

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

scholarly journals Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 128
Author(s):  
Zhihua Zhu ◽  
Zhaonian Yang ◽  
Xiaomei Fan ◽  
Yingtao Zhang ◽  
Juin Jei Liou ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Potential Candidate ◽  
Protection Scheme ◽  
Esd Protection ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

Computer-Aided Design and Applications of Planar Branch-Line Coupler Circuits

2020 ◽  
pp. 1-63
Author(s):  
Kok Yeow You ◽  
Nadera Najib Al-Areqi ◽  
Chia Yew Lee ◽  
Yeng Seng Lee
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Power Measurement ◽  
Design Guideline ◽  
Analytical Analysis ◽  
Branch Line ◽  
Initial Design ◽  
Mode Decomposition ◽  
Aided Design

This book chapter mainly focuses on analytical analysis for the branch-line coupler in which this method provides an explicit solution in the coupler design. Generally, the directional coupler is one of the fundamental components for Microwave Integrated Circuit (MIC), especially the equal power-split coupler that is used for signal monitoring, power measurement, power division, and balanced-type components such as balanced mixers. In this chapter, several applications of the branch-line coupler are also described. The analytical and design formulations of the coupler are derived based on ABCD matrix, transmission line principle, and even-odd mode decomposition. Although the simple analytical analysis is not sufficiently implemented in complex coupler structure, it is capable of providing an initial design guideline for the coupler dimensions. The initial design of the coupler dimensions based on analytical analysis can be gradually modified and optimized to achieve the desired size or performance of the coupler using advanced numerical simulation.

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