scholarly journals Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 887
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Circuit Simulation ◽  
Electrical Coupling ◽  
Ring Oscillator ◽  
Model Parameters ◽  
Flip Flop ◽  
Circuit Simulator ◽  
Aided Design ◽  
Better Than

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

scholarly journals Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

Micromachines ◽  
2019 ◽  
Vol 10 (10) ◽  
pp. 637 ◽  
Author(s):  
Ahn ◽  
Choi ◽  
Lim ◽  
Yu
Keyword(s):  
Computer Aided Design ◽  
Cell Model ◽  
Circuit Simulation ◽  
Electrical Coupling ◽  
Random Access ◽  
Bottom Layer ◽  
Logic Circuits ◽  
Unit Cell ◽  
Unit Cell Model ◽  
Flip Flop

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

scholarly journals Evaluation of the Feasibility of NaCaPO4-Blended Zirconia as a New CAD/CAM Material for Dental Restoration

Materials ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 3819
Author(s):  
Ting-Hsun Lan ◽  
Yu-Feng Chen ◽  
Yen-Yun Wang ◽  
Mitch M. C. Chou
Keyword(s):  
Computer Aided Design ◽  
Optical Microscope ◽  
Dental Restoration ◽  
Numerical Control ◽  
Test Results ◽  
Cnc Machine ◽  
Computer Aided ◽  
Cad Cam ◽  
Aided Design ◽  
Better Than

The computer-aided design/computer-aided manufacturing (CAD/CAM) fabrication technique has become one of the hottest topics in the dental field. This technology can be applied to fixed partial dentures, removable dentures, and implant prostheses. This study aimed to evaluate the feasibility of NaCaPO4-blended zirconia as a new CAD/CAM material. Eleven different proportional samples of zirconia and NaCaPO4 (xZyN) were prepared and characterized by X-ray diffractometry (XRD) and Vickers microhardness, and the milling property of these new samples was tested via a digital optical microscope. After calcination at 950 °C for 4 h, XRD results showed that the intensity of tetragonal ZrO2 gradually decreased with an increase in the content of NaCaPO4. Furthermore, with the increase in NaCaPO4 content, the sintering became more obvious, which improved the densification of the sintered body and reduced its porosity. Specimens went through milling by a computer numerical control (CNC) machine, and the marginal integrity revealed that being sintered at 1350 °C was better than being sintered at 950 °C. Moreover, 7Z3N showed better marginal fit than that of 6Z4N among thirty-six samples when sintered at 1350 °C (p < 0.05). The milling test results revealed that 7Z3N could be a new CAD/CAM material for dental restoration use in the future.

scholarly journals Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 852
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Propagation Delay ◽  
Channel Length ◽  
Memory Window ◽  
Switching Voltage ◽  
Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

scholarly journals Device Design Assessment of GaN Merged P-i-N Schottky Diodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1550 ◽  
Author(s):  
Yuliang Zhang ◽  
Xing Lu ◽  
Xinbo Zou
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
Background Concentration ◽  
Model Parameters ◽  
Design Assessment ◽  
Blocking Voltage ◽  
Aided Design ◽  
Drift Layer

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study their influence on the device’s performance. Extending the inter-p-GaN region distance or the Schottky contact portion could enhance the forward conduction capability; however, this leads to compromised electrical field screening effects from neighboring PN junctions, as well as reduced breakdown voltage. By reducing the drift layer background concentration, a higher breakdown voltage was expected for MPSs, as a larger portion of the drift layer itself could be depleted for sustaining vertical reverse voltage. However, lowering the drift layer concentration would also result in a reduction in forward conduction capability. The method and results of this study provide a guideline for designing MPS diodes with target blocking voltage and forward conduction at a low bias.

Microsensors for physical signals: Principles, device design, and fabrication technologies

1996 ◽  
Vol 74 (S1) ◽  
pp. 115-130 ◽  
Author(s):  
Arokia Nathan
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Electrical Signal ◽  
Single Chip ◽  
Research Activity ◽  
Rapid Pace ◽  
Silicon Based ◽  
Aided Design ◽  
New Generation ◽  
Physical And Chemical

Microsensors are miniaturized devices, fabricated using silicon-based and related technologies, that convert input physical and chemical signals into an output electrical signal. The key driving force in microsensor research has been the integrated circuit (IC) and micromachining technologies. The latter, in particular, is fueling tremendous activity in micro-electromechanical systems (MEMS). In terms of technology and design tools, MEMS is at a stage where microelectronics was 30 years ago and is expected to evolve at an equally rapid pace. The synergy between the IC, micromachining, and integrated photonics technologies can potentially spawn a new generation of microsystems that will feature a unique marriage of microsensor, signal-conditioning and -processing circuitry, micromechanics, and optomechanics possibly on a single chip. In this paper, the physical transduction principles, materials considerations, process-fabrication technologies, and computer-aided-design (CAD) tools will be reviewed along with pertinent examples drawn from our microsensor research activity at the Microelectronics Laboratory, University of Waterloo.

Up Close: The Interuniversity Microelectronics Center (IMEC), Leuven, Belgium

MRS Bulletin ◽  
1989 ◽  
Vol 14 (6) ◽  
pp. 35-38 ◽  
Author(s):  
Dirk Denoyelle
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Systems Design ◽  
System Level ◽  
Clean Room ◽  
Integrated Circuit Design ◽  
Processing Technologies ◽  
Wide Range ◽  
Application Specific Integrated Circuit ◽  
Aided Design

The Interuniversity Microelectronics Center, Leuven, Belgium (IMEC) is one of the world's largest independent research centers for microelectronics. It was established in 1984 by the Flemish government as a part of a comprehensive program to promote high technology in Flanders, Belgium. Benefiting from existing experience available mainly at the University of Leuven, IMEC moved into its present facilities in 1986 (Figure 1).The Center covers a wide range of research topics in the microelectronics domain—VLSI systems design methodologies, advanced semiconductor processing, materials, packaging, and more.About 50 people work on computer-aided design, developing a series of “true” silicon compilers: CATHEDRAL. With this software, ASIC (application specific integrated circuit) design becomes extremely attractive, since CATHEDRAL covers design from the high system level down to layout.INVOMEC, the training division of IMEC, supports universities in ASIC design. It trains people for both educational institutes and industry in chip design, makes available the necessary software, and has a well-established Multi Project Chip—Multi Project Wafer service.The Processing Technologies and Materials Divisions involve about 200 people and have a 3,600 m2 clean room at their disposal. The clean room consists of a 20% class 10 area with a fast-turnaround prototyping line and an 80% class 1000 area.IMEC's objectives are: to perform research in the microelectronics field, supporting both industry and universities, and to stimulate the microelectronics industry in Flanders.IMEC performs research on both silicon and III-V technologies.

Sensitivity Analysis Application for Multibody System Synthesis

2013 ◽  
Vol 420 ◽  
pp. 68-73 ◽  
Author(s):  
Alžbeta Sapietová ◽  
Milan Sapieta ◽  
Bohuslav Hyben
Keyword(s):  
Computer Aided Design ◽  
Multibody System ◽  
Simulation Software ◽  
Computational Techniques ◽  
Model Parameters ◽  
Technical Problems ◽  
Analysis Application ◽  
Aided Design ◽  
Short Time ◽  
Operating Regimes

Nowadays computational techniques utilization is essential part of the technical development. Visual form of data acquisition from simulations or solving of technical problems is the most effective approach. In the field of computer-aided design (CAD) 3D graphic visualization is certaintybecause it makes it possible to design a very complicated parts and devices at a short time. Furthermore it enable to trace how these parts behave during operating regimes and make an optimization of required parameters. In this paper the engineering design of gravity orienting part tool for cylindrical bushings will be presented. Each of 3D components was designed in CAD software Pro/ENGINEER and MSC.ADAMS virtual prototype was created in simulation software. Using the tools of parametric analysis for refining model parameters in software MSC.ADAMS optimization of selected design and dynamic parameters of given designed system was carried out.

scholarly journals Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 476 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Shupeng Chen ◽  
Wei Li ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Source Region ◽  
Ultra Low Power ◽  
Narrow Bandgap ◽  
Order Of Magnitude ◽  
Drain Region ◽  
Aided Design

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

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