scholarly journals A Novel Seedless TSV Process Based on Room Temperature Curing Silver Nanowires ECAs for MEMS Packaging

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 351 ◽  
Author(s):  
Meng ◽  
Cheng ◽  
Yang ◽  
Sun ◽  
Luo
Keyword(s):  
Room Temperature ◽  
Microelectromechanical Systems ◽  
Silver Nanowires ◽  
Low Cost ◽  
Mems Devices ◽  
Filling Process ◽  
Conductive Adhesives ◽  
Mems Packaging ◽  
Wide Range ◽  
High Efficient

The through-silicon-vias (TSVs) process is a vital technology in microelectromechanical systems (MEMS) packaging. The current via filling technique based on copper electroplating has many shortcomings, such as involving multi-step processes, requiring sophisticated equipment, low through-put and probably damaging the MEMS devices susceptible to mechanical polishing. Herein, a room temperature treatable, high-efficient and low-cost seedless TSV process was developed with a one-step filling process by using novel electrically conductive adhesives (ECAs) filled with silver nanowires. The as-prepared ECAs could be fully cured at room temperature and exhibited excellent conductivity due to combining the benefits of both polymethyl methacrylate (PMMA) and silver nanowires. Complete filling of TSVs with the as-prepared 30 wt% silver nanowires ECAs was realized, and the resistivity of a fully filled TSV was as low as 10−3 Ω·cm. Furthermore, the application of such novel TSV filling process could also be extended to a wide range of different substrates, showing great potential in MEMS packaging, flexible microsystems and many other applications.

The IP Landscape for MEMS Packaging

2009 ◽  
Author(s):  
Charles E. Bauer ◽  
Raymond A. Fillion ◽  
Herbert J. Neuhaus ◽  
Marc Papageorge
Keyword(s):  
Citation Analysis ◽  
Strategic Alliance ◽  
Market Development ◽  
Mems Devices ◽  
Strategic Framework ◽  
Mems Packaging ◽  
Thermal Requirements ◽  
Unique Mapping ◽  
Wide Range ◽  
On Line

Early MEMS devices employed packages developed for conventional semiconductor microelectronics. Today, MEMS packages reflect the unique environment, mechanical, chemical and thermal requirements of MEMS devices themselves. A casual search of on-line databases reveals nearly 40,000 patents worldwide containing the words “MEMS” and “package.” While not all relevant, the number of IP documents easily overwhelms researchers, investors and IP practitioners. The authors systematically analyze the relevant IP and organize it by generic technology categories. A unique mapping methodology provides greater understanding of the landscape of IP in the MEMS packaging arena across a wide range of considerations including geography, IP development and ownership trends, infrastructure implications and application concepts. The authors also present a rudimentary valuation of IP within the MEMS packaging field based on citation analysis. Finally, the authors demonstrate a method to develop a strategic framework based on the IP landscape useful for investment, market development and strategic alliance planning.

μCHILL: a lightweight, modular system for handling crystalline samples at low temperatures under inert conditions

2018 ◽  
Vol 51 (2) ◽  
pp. 541-548 ◽  
Author(s):  
Michael Solar ◽  
Nils Trapp
Keyword(s):  
Low Temperatures ◽  
Room Temperature ◽  
Low Cost ◽  
Three Dimensional ◽  
Modular System ◽  
Preparation Time ◽  
Stable Conditions ◽  
Wide Range ◽  
Single Operator ◽  
Cold Gas

A procedure for preparing and mounting crystals under inert conditions is demonstrated, using a specialized apparatus (μCHILL) to provide a cold gas stream fed from a liquid nitrogen (LN2) reservoir or an open bath heat exchanger. A second, dry gas stream at room temperature enwraps the cold gas, protecting the sample preparation zone from ambient moisture. The technique is extremely flexible, requiring only a single operator, little practice and almost no preparation time. The device enables operation in a wide temperature range (at least 213 K to room temperature), providing temperature control and very stable conditions with no icing for extended time periods. The flexible, modular and low-cost design is based on three-dimensional-printed parts and readily available standard components, potentially making the device available to a wide range of users and applications not limited to single-crystal studies.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing

2013 ◽  
Vol 2013 (1) ◽  
pp. 000001-000006
Author(s):  
F. Roozeboom ◽  
M. Smets ◽  
B. Kniknie ◽  
M. Hoppenbrouwers ◽  
G. Dingemans ◽  
...  
Keyword(s):  
High Speed ◽  
Room Temperature ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Industrial Process ◽  
Atomic Layer ◽  
Single Step ◽  
Thermal Mode ◽  
Different Types ◽  
Sidewall Passivation

The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10–20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing. For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use Laser-Induced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.

scholarly journals Direct-Write Dewetting of High Melting Temperature Metals on Flexible Substrates

2019 ◽  
Vol 9 (15) ◽  
pp. 3165
Author(s):  
Anthony J. Ferrer ◽  
Anna Halajko ◽  
Glenn G. Amatucci
Keyword(s):  
Thin Films ◽  
Melting Temperature ◽  
Near Infrared ◽  
Microelectromechanical Systems ◽  
Modern Technology ◽  
Direct Write ◽  
High Melting ◽  
Mems Devices ◽  
High Melting Temperature ◽  
Wide Range

Microelectromechanical systems (MEMS) are pervasive in modern technology due to their reliability, small foot print, and versatility of function. While many of the manufacturing techniques for MEMS devices stem from integrated circuit (IC) manufacturing, the wide range of designs necessitates more varied processing techniques. Here, new details of a scanning laser based direct-write dewetting technique are presented as an expansion of previous demonstrations. For the first time, the ability to pattern a high melting temperature and high reflectance metallic thin films of Ni and Ag, respectively, on polymer substrates is reported. Novel methods for reducing the power necessary for processing highly reflective films are demonstrated by depositing very thin films of high near-infrared absorbance.

‘On-water’ organic synthesis: a green, highly efficient, low cost and reusable catalyst system for biaryl synthesis under aerobic conditions at room temperature

RSC Advances ◽  
2015 ◽  
Vol 5 (63) ◽  
pp. 50655-50659 ◽  
Author(s):  
Bishwajit Saikia ◽  
Preeti Rekha Boruah ◽  
Abdul Aziz Ali ◽  
Diganta Sarma
Keyword(s):  
Organic Synthesis ◽  
Room Temperature ◽  
Low Cost ◽  
Suzuki Reaction ◽  
Catalyst System ◽  
Reusable Catalyst ◽  
Wide Range ◽  
Biaryl Synthesis ◽  
Phenylboronic Acids ◽  
Operational Simplicity

The PdCl2/sucrose/K2CO3/H2O system showed the superb catalytic activity towards the Suzuki reaction of a wide range of aryl/heteroaryl halides with diverse phenylboronic acids at room temperature with operational simplicity and shorter reaction time.

A Review on Laser Processing in Electronic and MEMS Packaging

2017 ◽  
Vol 139 (3) ◽  
Author(s):  
Kaysar Rahim ◽  
Ahsan Mian
Keyword(s):  
Laser Processing ◽  
Microelectromechanical Systems ◽  
Mechanical Effect ◽  
Future Trend ◽  
Small Scale ◽  
Attractive Alternative ◽  
Mems Devices ◽  
Processing Technologies ◽  
Mems Packaging ◽  
Heating And Cooling

The packaging of electronic and microelectromechanical systems (MEMS) devices is an important part of the overall manufacturing process as it ensures mechanical robustness as well as required electrical/electromechanical functionalities. The packaging integration process involves the selection of packaging materials and technology, process design, fabrication, and testing. As the demand of functionalities of an electronic or MEMS device is increasing every passing year, chip size is getting larger and is occupying the majority of space within a package. This requires innovative packaging technologies so that integration can be done with less thermal/mechanical effect on the nearby components. Laser processing technologies for electronic and MEMS packaging have potential to obviate some of the difficulties associated with traditional packaging technologies and can become an attractive alternative for small-scale integration of components. As laser processing involves very fast localized and heating and cooling, the laser can be focused at micrometer scale to perform various packaging processes such as dicing, joining, and patterning at the microscale with minimal or no thermal effect on surrounding material or structure. As such, various laser processing technologies are currently being explored by researchers and also being utilized by electronic and MEMS packaging industries. This paper reviews the current and future trend of electronic and MEMS packaging and their manufacturing processes. Emphasis is given to the laser processing techniques that have the potential to revolutionize the future manufacturing of electronic and MEMS packages.

Developments in Microelectromechanical Systems (MEMS): A Manufacturing Perspective

2003 ◽  
Vol 125 (4) ◽  
pp. 816-823 ◽  
Author(s):  
Srinivas A. Tadigadapa ◽  
Nader Najafi
Keyword(s):  
Microelectromechanical Systems ◽  
Process Development ◽  
Reliability Testing ◽  
Mems Devices ◽  
Manufacturing Strategy ◽  
Cad Tools ◽  
Fragile State ◽  
Mems Packaging ◽  
Overall Performance

This paper presents a discussion of some of the major issues that need to be considered for the successful commercialization of MEMS products. The diversity of MEMS devices and historical reasons have led to scattered developments in the MEMS manufacturing infrastructure. A good manufacturing strategy must include the complete device plan including package as part of the design and process development of the device. In spite of rapid advances in the field of MEMS there are daunting challenges that lie in the areas of MEMS packaging, and reliability testing. CAD tools for MEMS are starting to get more mature but are still limited in their overall performance. MEMS manufacturing is currently at a fragile state of evolution. In spite of all the wonderful possibilities, very few MEMS devices have been commercialized. In our opinion, the magnitude of the difficulty of fabricating MEMS devices at the manufacturing level is highly underestimated by both the current and emerging MEMS communities. A synopsis of MEMS manufacturing issues is presented here.

Interconnect Technologies for Heterogeneous 3D Integration : CMOS and MEMS

2010 ◽  
Vol 1249 ◽  
Author(s):  
Hyung Suk Yang ◽  
Muhannad Bakir
Keyword(s):  
High Performance ◽  
Electronic Circuit ◽  
Microelectromechanical Systems ◽  
High Density ◽  
Mems Devices ◽  
New Materials ◽  
3D Integration ◽  
Through Silicon Via ◽  
Wide Range ◽  
Conventional Methods

AbstractMicroelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.

Functional Fiber Junctions for Circuit Routing in E-Textiles: Deterministic Alignment of MEMS Layout With Fabric Structure

2021 ◽  
Author(s):  
Sushmita Challa ◽  
M. Shafquatul Islam ◽  
Danming Wei ◽  
Jasmin Beharic ◽  
Dan O. Popa ◽  
...  
Keyword(s):  
Microelectromechanical Systems ◽  
Flexible Substrate ◽  
Fibrous Materials ◽  
Mems Devices ◽  
Image Processing Algorithm ◽  
Mems Packaging ◽  
Alignment Procedure ◽  
Fabric Structure ◽  
Parallel Transfer ◽  
Functional Fiber

Abstract Fabrics and fibrous materials offer a soft, porous, and flexible substrate for microelectromechanical systems (MEMS) packaging in breathable, wearable formats that allow airflow. Device-on-fiber systems require developments in the field of E-Textiles including smart fibers, functional fiber intersections, textile circuit routing, and alignment methods that adapt to irregular materials. In this paper, we demonstrate a MEMS-on-fabric layout workflow that obtains fiber intersection locations from high-resolution fabric images. We implement an image processing algorithm to drive the MEMS layout software, creating an individualized MEMS “gripper” layout designed to grasp fibers on a specific fabric substrate during a wafer-to-fabric parallel transfer step. The efficiency of the algorithm in terms of a number of intersections identified on the complete image is analyzed. The specifications of the MEMS layout design such as the length of the MEMS gripper, spatial distribution, and orientation are derivable from the MATLAB routine implemented on the image. Furthermore, the alignment procedure, tolerance, and hardware setup for the alignment method of the framed sample fabric to the wafer processed using the custom gripper layout are discussed along with the challenges of the release of MEMS devices from the Si substrate to the fabric substrate.

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