Interconnect Technologies for Heterogeneous 3D Integration : CMOS and MEMS

2010 ◽  
Vol 1249 ◽  
Author(s):  
Hyung Suk Yang ◽  
Muhannad Bakir
Keyword(s):  
High Performance ◽  
Electronic Circuit ◽  
Microelectromechanical Systems ◽  
High Density ◽  
Mems Devices ◽  
New Materials ◽  
3D Integration ◽  
Through Silicon Via ◽  
Wide Range ◽  
Conventional Methods

AbstractMicroelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

scholarly journals Direct-Write Dewetting of High Melting Temperature Metals on Flexible Substrates

2019 ◽  
Vol 9 (15) ◽  
pp. 3165
Author(s):  
Anthony J. Ferrer ◽  
Anna Halajko ◽  
Glenn G. Amatucci
Keyword(s):  
Thin Films ◽  
Melting Temperature ◽  
Near Infrared ◽  
Microelectromechanical Systems ◽  
Modern Technology ◽  
Direct Write ◽  
High Melting ◽  
Mems Devices ◽  
High Melting Temperature ◽  
Wide Range

Microelectromechanical systems (MEMS) are pervasive in modern technology due to their reliability, small foot print, and versatility of function. While many of the manufacturing techniques for MEMS devices stem from integrated circuit (IC) manufacturing, the wide range of designs necessitates more varied processing techniques. Here, new details of a scanning laser based direct-write dewetting technique are presented as an expansion of previous demonstrations. For the first time, the ability to pattern a high melting temperature and high reflectance metallic thin films of Ni and Ag, respectively, on polymer substrates is reported. Novel methods for reducing the power necessary for processing highly reflective films are demonstrated by depositing very thin films of high near-infrared absorbance.

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000939-000957
Author(s):  
Florian Herrault ◽  
M. Yajima ◽  
M. Chen ◽  
C. McGuire ◽  
A. Margomenos
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Silicon Wafers ◽  
High Resistivity ◽  
3D Integration ◽  
Passive Components ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Lift Off ◽  
Rf Inductors

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.

scholarly journals Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via

Sensors ◽  
2018 ◽  
Vol 19 (1) ◽  
pp. 93 ◽  
Author(s):  
Meng Zhang ◽  
Jian Yang ◽  
Yurong He ◽  
Fan Yang ◽  
Fuhua Yang ◽  
...  
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Three Dimensional ◽  
Fabrication Process ◽  
Anodic Bonding ◽  
Mems Sensors ◽  
Through Silicon Via ◽  
Hermetic Packaging ◽  
Order Of Magnitude ◽  
Capacitive Mems

A novel three-dimensional (3D) hermetic packaging technique suitable for capacitive microelectromechanical systems (MEMS) sensors is studied. The composite substrate with through silicon via (TSV) is used as the encapsulation cap fabricated by a glass-in-silicon (GIS) reflow process. In particular, the low-resistivity silicon pillars embedded in the glass cap are designed to serve as the electrical feedthrough and the fixed capacitance plate at the same time to simplify the fabrication process and improve the reliability. The fabrication process and the properties of the encapsulation cap were studied systematically. The resistance of the silicon vertical feedthrough was measured to be as low as 263.5 mΩ, indicating a good electrical interconnection property. Furthermore, the surface root-mean-square (RMS) roughnesses of glass and silicon were measured to be 1.12 nm and 0.814 nm, respectively, which were small enough for the final wafer bonding process. Anodic bonding between the encapsulation cap and the silicon wafer with sensing structures was conducted in a vacuum to complete the hermetic encapsulation. The proposed packaging scheme was successfully applied to a capacitive gyroscope. The quality factor of the packaged gyroscope achieved above 220,000, which was at least one order of magnitude larger than that of the unpackaged. The validity of the proposed packaging scheme could be verified. Furthermore, the packaging failure was less than 1%, which demonstrated the feasibility and reliability of the technique for high-performance MEMS vacuum packaging.

Optimizing Stressor Film Deposition Sequence in Polish Rate Order for Best Planarization

2011 ◽  
Vol 1335 ◽  
Author(s):  
John H Zhang ◽  
Changyong Xiao ◽  
Jay W Strane ◽  
Rajasekhar Venigalla ◽  
Laertis Economikos ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Film Deposition ◽  
3D Integration ◽  
Stress Gradients ◽  
Technology Node ◽  
Key Technologies ◽  
Polish Rate

ABSTRACTChemical Mechanical Polish (CMP) is one of the key technologies for the development of modern high performance integrated circuits. The requirements for the CMP uniformity get extremely demanding in order to meet the litho requirements for 32nm technology node and beyond. In this paper, two kinds of orders related to the stressor films that affect the CMP uniformity are revealed. The first is the stressor films deposition order according to the CMP polish rate of each stressor film. The second is the stress gradients order that formed inside the films sitting on top of the stressors. Through the optimization of the order, we show successfully removal of couple hundreds angstroms stressor step heights within 300mm wafer range. The method developed here can also find applications in microelectromechanical systems and 3D integration circuits.

3D High Density: technology, roadmap and applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Lucile Arnaud ◽  
Severine Cheramy ◽  
Amandine Jouve ◽  
Lucile Arnaud ◽  
Claire Fenouillet ◽  
...  
Keyword(s):  
High Performance ◽  
Gas Sensing ◽  
High Mobility ◽  
High Density ◽  
Integration Scheme ◽  
Back Side ◽  
3D Integration ◽  
Contact Density ◽  
Test Vehicle ◽  
Sensing Applications

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions. Additionally, difficulty of associating in a same 2D wafer heterogeneous processes (ie: combining Cmos device with “exotic” material, with low temperature dielectric) also gives an opportunity for a high density 3D approach rather than a 2D one. As an example, back-side illuminated imagers (BSI Imagers) players have recently released such 3D density (pitch in the range of 5 to 10 micron) [1] � From now, thinking about a 3D industrial integration within the range of few microns pitch is not anymore a dream. This specific application may raise some interest for other products such as memory denser stacking, partitioning of a large SoC � The objective of the paper is to describe 2 complementary technologies developed at CEA-Leti which address such high density of 3D integration: Hybrid Bonding in the range of few �ms; Coolcube in the range of few 100e of nms. We will first take some time to describe both technologies and recent CEA-Leti's results. The positioning of each technologies in terms of pitch and performance will be given. 1 - 3D parallel integration: hybrid bonding Hybrid bonding integration scheme has been first developed on a wafer scale approach. A test vehicle, with several BEOL layers and connected by the implementation of hybrid bonding, has been designed. Morphological and electrical data will be given leading to the conclusion that the process is very reliable and robust [1], [2]. Contact resistance per contact pads has been measured at few mOhms, which is relatively low compared to tens or even hundreds of mOhms for more classical interconnection technologies (copper pillar, bump, Cu-Cu thermos-compression). Nevertheless, for cost reason, as well as for multi dies stacking, the need for Die-To-Wafer approach remains true, while keeping a high density of interconnect [3]. The process flow as well as test vehicle designed for this approach will be described. Major challenges including handling of the dies after sawing and till the bonding itself will be addressed in the paper: wafer handler, wafer preparation and pick & place. Deep characterization is proposed. 2 - 3D sequential integration: CoolCube An alternative approach to conventional planar integration for future nodes is the monolithic 3D integration (3DVLSI). Monolithic offers the possibility to stack devices with a lithographic alignment precision enabling 3D contacts introduction at the device level (up to 100 million vias per mm� with 14nm ground rules). 3DVLSI can by routed either at gate or transistor levels. The partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. Partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [4–5]) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III–V nFETs above SiGe pFETs [6–7]. These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI, with its high contact density, can also be seen as a powerful solution for heterogeneous co-integrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [8–9] or highly miniaturized imagers [10]. 3- Comparison and roadmap This paper will also provide features that give some applications' meaning for the development of both technologies in parallel. Particularly, both technologies will be compared in terms of possible pitch reachable. Main comparison features rely on advanced interconnection: dimension & pitch resistance, parasite. A thermal simulation comparison study will also be included.

Electronic Materials and Structures for Multichip Modules

1992 ◽  
Vol 114 (2) ◽  
pp. 226-233 ◽  
Author(s):  
H. K. Charles
Keyword(s):  
Systematic Review ◽  
Electronic Properties ◽  
High Performance ◽  
Electronic Materials ◽  
Electronic Devices ◽  
High Density ◽  
Multichip Module ◽  
Multichip Modules ◽  
New Materials ◽  
Potential Impact

Multichip modules are rapidly becoming a major thrust in electronic packaging technology. Because of the high density and high performance nature of the electronic devices packaged in multichip modules, stringent new demands are being placed on materials, interconnect, and packaging structures. A systematic review of the materials and material structures for multichip modules is presented along with their associated physical and electronic properties. Particular emphasis is placed on new materials and their potential impact on multichip module packaging. Examples of their use in the fabrication of multichip modules and advanced chip-on-board systems are described.

High Mobility Channel Materials and Novel Devices for Scaling of Nanoelectronics beyond the Si Roadmap

2009 ◽  
Vol 1194 ◽  
Author(s):  
Marc Heyns ◽  
Florence Bellenger ◽  
Guy Brammertz ◽  
Matty Caymax ◽  
Stefan De Gendt ◽  
...  
Keyword(s):  
High Performance ◽  
Density Functional ◽  
High Mobility ◽  
Superior Performance ◽  
New Materials ◽  
New Device ◽  
High K ◽  
Wide Range ◽  
High Mobility Channel ◽  
Novel Devices

AbstractHigh mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface. Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

scholarly journals A Novel Seedless TSV Process Based on Room Temperature Curing Silver Nanowires ECAs for MEMS Packaging

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 351 ◽  
Author(s):  
Meng ◽  
Cheng ◽  
Yang ◽  
Sun ◽  
Luo
Keyword(s):  
Room Temperature ◽  
Microelectromechanical Systems ◽  
Silver Nanowires ◽  
Low Cost ◽  
Mems Devices ◽  
Filling Process ◽  
Conductive Adhesives ◽  
Mems Packaging ◽  
Wide Range ◽  
High Efficient

The through-silicon-vias (TSVs) process is a vital technology in microelectromechanical systems (MEMS) packaging. The current via filling technique based on copper electroplating has many shortcomings, such as involving multi-step processes, requiring sophisticated equipment, low through-put and probably damaging the MEMS devices susceptible to mechanical polishing. Herein, a room temperature treatable, high-efficient and low-cost seedless TSV process was developed with a one-step filling process by using novel electrically conductive adhesives (ECAs) filled with silver nanowires. The as-prepared ECAs could be fully cured at room temperature and exhibited excellent conductivity due to combining the benefits of both polymethyl methacrylate (PMMA) and silver nanowires. Complete filling of TSVs with the as-prepared 30 wt% silver nanowires ECAs was realized, and the resistivity of a fully filled TSV was as low as 10−3 Ω·cm. Furthermore, the application of such novel TSV filling process could also be extended to a wide range of different substrates, showing great potential in MEMS packaging, flexible microsystems and many other applications.

scholarly journals Novel Test Fixture for Characterizing MEMS Switch Microcontact Reliability and Performance

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 579 ◽  
Author(s):  
Protap Mahanta ◽  
Farhana Anwar ◽  
Ronald Coutu
Keyword(s):  
Microelectromechanical Systems ◽  
Electrical Contact ◽  
Mems Devices ◽  
Closing Time ◽  
Test Fixture ◽  
Mems Switches ◽  
Mems Switch ◽  
Wide Range ◽  
And Performance ◽  
Hot Switching

In microelectromechanical systems (MEMS) switches, the microcontact is crucial in determining reliability and performance. In the past, actual MEMS devices and atomic force microscopes (AFM)/scanning probe microscopes (SPM)/nanoindentation-based test fixtures have been used to collect relevant microcontact data. In this work, we designed a unique microcontact support structure for improved post-mortem analysis. The effects of contact closure timing on various switching conditions (e.g., cold-switching and hot-switching) was investigated with respect to the test signal. Mechanical contact closing time was found to be approximately 1 us for the contact force ranging from 10–900 μN. On the other hand, for the 1 V and 10 mA circuit condition, electrical contact closing time was about 0.2 ms. The test fixture will be used to characterize contact resistance and force performance and reliability associated with wide range of contact materials and geometries that will facilitate reliable, robust microswitch designs for future direct current (DC) and radio frequency (RF) applications.

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