scholarly journals Design and Analysis of Multiplexer Based 4-Bit Flash ADC

2019 ◽  
Vol 8 (6S2) ◽  
pp. 797-802
Keyword(s):  
Analog Circuits ◽  
Processing Speed ◽  
Power Dissipation ◽  
Sampling Rate ◽  
Chip Area ◽  
Flash Adc ◽  
Input Signals ◽  
Low Power Dissipation ◽  
Ladder Network ◽  
Tiq Comparator

In reality, signals exist in analog format. The digital circuits are more convenient than analog circuits with respect to processing speed and efficiency in transmission. Hence there is a great demand for ADC converters. The typical Flash ADC contains resistor ladder circuit, comparator and code converter. The most advantageous parameter of Flash ADC is its speed. Hence it can be used in variety of applications such as micro electronics, wireless sensor networks, transceivers. Flash ADC still suffers from minimum resolution and consumes large amount of power. However these are due to its complexity in terms of chip area requirement in comparison with other ADCs. This new technique of four bit Flash ADC using TIQ comparator is implemented here. Here, a comparison is brought between the input signals with internal built threshold using TIQ comparators. It avoids the too much resistor usage in ladder network. In general, 2N -1 number of TIQ comparators is required to design N-bit flash ADC. TIQ output was encoded into binary by an encoder. A new MUX based encoding technique has been used to enhance the conversion speed for achieving highest sampling rate with low power dissipation. The design is simulated in Mentor Graphics environment using 130nm technology and result shows a deep reduce in the power consumption i.e.0.833µW and conversion speed 15.393ns for 4-bit ADC.

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

2019 ◽  
Vol 28 (08) ◽  
pp. 1950125
Author(s):  
Jianqun Ding ◽  
Lijun Huang ◽  
Xianwu Mi ◽  
Dajiang He ◽  
Shenghai Chen ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Low Power Dissipation ◽  
Feedback Structure ◽  
Voltage Swing ◽  
Low Supply Voltage ◽  
Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC

2016 ◽  
Vol 26 (03) ◽  
pp. 1750046 ◽  
Author(s):  
Prachi Palsodkar ◽  
Pravin Dakhole ◽  
Prasanna Palsodkar
Keyword(s):  
Low Voltage ◽  
Size Variation ◽  
Standard Cell ◽  
Hardware Complexity ◽  
Large Area ◽  
Flash Adc ◽  
Low Voltage Operation ◽  
Division Theorem ◽  
Ladder Network ◽  
Tiq Comparator

This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using the proposed comparator requires 206 minimum-sized transistors and provides large area saving compared to previously proposed designs. Thermometer code is partitioned using algebraic division theorem. This conversion is used for mathematical modeling and complexity reduction of decoder circuit using semi-parallel organization of comparators. Circuit is designed using 90 nm technology which exhibits satisfactory performance even in process variation.

A Fully-Integrated D-Band Frequency Synthesizer in 0.13-μm SiGe BiCMOS

2015 ◽  
Vol 25 (01) ◽  
pp. 1640010
Author(s):  
Jin He ◽  
Yong-Zhong Xiong ◽  
Jiankang Li ◽  
Muthukumaraswamy Annamalai Arasu ◽  
Yue Ping Zhang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Frequency Synthesizer ◽  
Frequency Multiplier ◽  
Band Frequency ◽  
Chip Area ◽  
Fully Integrated ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Low Power Dissipation

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-[Formula: see text]m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler ([Formula: see text][Formula: see text]2) and a quadrupler ([Formula: see text][Formula: see text]4). The FS generates the D-band output signals from 164.08 to 166.19[Formula: see text]GHz. At 166.19[Formula: see text]GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are [Formula: see text]54.07[Formula: see text]dBc/Hz and [Formula: see text]72.29[Formula: see text]dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110[Formula: see text]mW and the chip area is [Formula: see text] including all testing pads. The FS has great potential to be used for low-power D-band applications.

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ring Counter ◽  
Low Power Dissipation

Research on PVDF Micro-Force Sensor

2014 ◽  
Vol 599-601 ◽  
pp. 1135-1138
Author(s):  
Chao Zhe Ma ◽  
Jin Song Du ◽  
Yi Yang Liu
Keyword(s):  
Power Dissipation ◽  
Polyvinylidene Fluoride ◽  
High Sensitivity ◽  
Force Sensor ◽  
Calibration Method ◽  
Pvdf Film ◽  
Force Sensors ◽  
Low Power Dissipation ◽  
Micro Force Sensor ◽  
Processing Circuit

At present, sub-micro-Newton (sub-μN) micro-force in micro-assembly and micro-manipulation is not able to be measured reliably. The piezoelectric micro-force sensors offer a lot of advantages for MEMS applications such as low power dissipation, high sensitivity, and easily integrated with piezoelectric micro-actuators. In spite of many advantages above, the research efforts are relatively limited compared to piezoresistive micro-force sensors. In this paper, Sensitive component is polyvinylidene fluoride (PVDF) and the research object is micro-force sensor based on PVDF film. Moreover, the model of micro-force and sensor’s output voltage is built up, signal processing circuit is designed, and a novel calibration method of micro-force sensor is designed to reliably measure force in the range of sub-μN. The experimental results show the PVDF sensor is designed in this paper with sub-μN resolution.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

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