scholarly journals Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

2020 ◽  
Vol 14 (05) ◽  
pp. 73 ◽  
Author(s):  
T. Suguna ◽  
M. Janaki Rani
Keyword(s):  
Mobile Applications ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Switching Activity ◽  
Ripple Carry Adder ◽  
Adiabatic Logic ◽  
Overall Performance ◽  
Power Delay Product ◽  
Research Domain

In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

scholarly journals Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool

2012 ◽  
pp. 155-158
Author(s):  
Samik Samanta
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Vlsi Circuits ◽  
Limiting Factor ◽  
Switching Activity ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Adiabatic Switching ◽  
Adiabatic Logic ◽  
Innovative Solutions

Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from it’s switching activity, which is mainly influenced by the supply voltage and effective capacitance.[1,2,3] To optimize power dissipation, the researches show various techniques like appropriate coding, appropriate design architectures, appropriate manipulation algorithms. In this paper we have applied adiabatic logic design approach to design COMS inverter. Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at a circuit and logic level achieve reduction in power [12] Various adiabatic logic based inverters are shown. Mainly our aim is to design and simulate PFAL inverters. Finally we have calculated dissipated power of static CMOS inverter and compare it with that of PFAL based inverter. [4, 6]

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection

2019 ◽  
Vol 11 (1) ◽  
pp. 80-87 ◽  
Author(s):  
Jitendra Kumar Saini ◽  
Avireni Srinivasulu ◽  
Renu Kumawat
Keyword(s):  
Mass Production ◽  
High Speed ◽  
Field Effect Transistor ◽  
Full Adder ◽  
Enabling Technology ◽  
Look Ahead ◽  
Ripple Carry Adder ◽  
Effect Transistor ◽  
Cad Tool ◽  
Power Delay Product

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

scholarly journals Energy Efficient GDI Based Full Adders For Computing Applications

2020 ◽  
Vol 4 (6) ◽  
pp. 5-9
Author(s):  
Bilal N Md ◽  
Bhaskara Rao K ◽  
Mohan Das S
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Low Power Consumption ◽  
Basic Logic ◽  
Power Delay Product ◽  
Full Swing

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

scholarly journals A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

2013 ◽  
Vol 7 (3) ◽  
pp. 1155-1165
Author(s):  
Dayadi Lakshmaiah ◽  
Dr. M.V. Subramanyam ◽  
Dr. K.Sathya Prasad
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Full Adder ◽  
High Threshold ◽  
Low Threshold ◽  
Supply Voltage Scaling ◽  
Critical Paths ◽  
Power Delay Product ◽  
Novel Design

This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

scholarly journals Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

2022 ◽  
Vol 2161 (1) ◽  
pp. 012050
Author(s):  
Imran Ahmed Khan
Keyword(s):  
High Speed ◽  
Full Adder ◽  
Logic Circuits ◽  
Power Efficient ◽  
Cmos Transistors ◽  
Bases Of Power ◽  
Ripple Carry Adder ◽  
Supply Voltages ◽  
Power Delay Product ◽  
Carbon Nano Tube

Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

An Energy Efficient Logic Approach to Implement CMOS Full Adder

2017 ◽  
Vol 26 (05) ◽  
pp. 1750084 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Supply Voltage ◽  
Signal Integrity ◽  
Full Adder ◽  
Cmos Technology ◽  
Nand Gate ◽  
Common Environment ◽  
Logic Approach ◽  
Power Delay Product

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90[Formula: see text]nm technology operating at 1.2[Formula: see text]V supply voltage and UMC 55[Formula: see text]nm CMOS technology operating at 1.0[Formula: see text]V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

CNFET Based Low Power Full Adder Circuit for VLSI Applications

2020 ◽  
Vol 10 (3) ◽  
pp. 286-291
Author(s):  
Inamul Hussain ◽  
Saurabh Chaudhury
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
New Device ◽  
Technology Node ◽  
Technological Advances ◽  
Power Delay Product ◽  
Technology Nodes

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250079
Author(s):  
BASHAR HADDAD ◽  
AMIN JARRAH
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Activity Analysis ◽  
Vlsi Circuits ◽  
Total Power ◽  
Switching Activity ◽  
Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

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