Suppress of Substrate-Assisted Depletion Effects in Super Junction LDMOS on Thin Film SOI

2013 ◽  
Vol 721 ◽  
pp. 521-526
Author(s):  
Chao Xia ◽  
Xin Hong Cheng ◽  
Zhong Jian Wang ◽  
Da Wei He ◽  
Duo Cao ◽  
...  
Keyword(s):  
Charge Density ◽  
Breakdown Voltage ◽  
Inversion Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Device Structure ◽  
Depletion Effect ◽  
Fabrication Procedure ◽  
A Charge

Conventional super-junction lateral double diffused MOSFET (SJ-LDMOS) fabricated on Silicon on Insulator (SOI) substrate suffers from low breakdown voltage under the same on-resistance due to substrate-assisted depletion effect. To suppress this effect, it is important to find the charge density in the inversion layer under buried oxide. In this paper, we propose a charge density equation and its formulation. The results were used in a 3D device simulator to optimize the device structure. The experimental results confirm that the equation is useful to optimize device performance. The breakdown voltage of structure increased 54% and on-state-resistance decreased 58% compared to conventional SJ device. The device fabrication procedure is fully compatible with mainstream SOI CMOS process.

Offset-Gate Structures for Increased Breakdown Voltages in Silicon-On-Insulator Transistors

1984 ◽  
Vol 33 ◽  
Author(s):  
C. I. Drowley ◽  
T. I. Kamins
Keyword(s):  
Charge Density ◽  
Breakdown Voltage ◽  
Silicon On Insulator ◽  
Fixed Charge ◽  
Back Surface ◽  
Mos Transistors ◽  
Fixed Charge Density ◽  
Gate Structure ◽  
High Fields ◽  
Overlap Region

ABSTRACTAn offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films. The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region. Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to 1×10″ cm−2.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Increased breakdown voltage of silicon-on-insulator Schottky diodes

1993 ◽  
Vol 29 (15) ◽  
pp. 1381 ◽  
Author(s):  
B.R. Kang ◽  
S.N. Yoon ◽  
Y.H. Cho ◽  
S.I. Cha ◽  
Y.I. Choi
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diodes ◽  
Silicon On Insulator

scholarly journals Ultrafast formation of domain walls of a charge density wave in SmTe3

2021 ◽  
Vol 103 (5) ◽  
Author(s):  
M. Trigo ◽  
P. Giraldo-Gallo ◽  
J. N. Clark ◽  
M. E. Kozina ◽  
T. Henighan ◽  
...  
Keyword(s):  
Charge Density ◽  
Charge Density Wave ◽  
Domain Walls ◽  
Density Wave ◽  
A Charge

Ultrafast switching to an insulating-like metastable state by amplitudon excitation of a charge density wave

2021 ◽  
Author(s):  
Naotaka Yoshikawa ◽  
Hiroki Suganuma ◽  
Hideki Matsuoka ◽  
Yuki Tanaka ◽  
Pierre Hemme ◽  
...  
Keyword(s):  
Charge Density ◽  
Metastable State ◽  
Charge Density Wave ◽  
Density Wave ◽  
Ultrafast Switching ◽  
A Charge

scholarly journals Ultrafast spot-profile LEED of a charge-density wave phase transition

2021 ◽  
Vol 118 (22) ◽  
pp. 221603
Author(s):  
G. Storeck ◽  
K. Rossnagel ◽  
C. Ropers
Keyword(s):  
Phase Transition ◽  
Charge Density ◽  
Charge Density Wave ◽  
Density Wave ◽  
Wave Phase ◽  
Charge Density Wave Phase ◽  
A Charge
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