15 kV, Large Area (1 cm2), 4H-SiC p-Type Gate Turn-Off Thyristors

2013 ◽  
Vol 740-742 ◽  
pp. 978-981 ◽  
Author(s):  
Lin Cheng ◽  
Anant K. Agarwal ◽  
Craig Capell ◽  
Michael J. O'Loughlin ◽  
Khiem Lam ◽  
...  
Keyword(s):  
High Voltage ◽  
Current Density ◽  
Large Area ◽  
Test Set ◽  
High Injection ◽  
Blocking Voltage ◽  
Set Up ◽  
P Type ◽  
Drift Layer ◽  
Injection Current Density

In this paper, we report our recently developed 1 cm2, 15 kV SiC p-GTO with an extremely low differential on-resistance (RON,diff) of 4.08 mΩ•cm2 at a high injection-current density (JAK) of 600 ~ 710 A/cm2. The 15 kV SiC p-GTO was built on a 120 μm, 2×1014/cm3 doped p-type SiC drift layer with a device active area of 0.521 cm2. Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the RON,diff at JAK of 600 ~ 710 A/cm2 decreased from 4.08 mΩ•cm2 at 20°C to 3.45 mΩ•cm2 at JAK of 600 ~ 680 A/cm2 at 200°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current at a VGK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Device Options and Design Considerations for High-Voltage (10-20 kV) SiC Power Switching Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1449-1452 ◽  
Author(s):  
Yang Sui ◽  
Ginger G. Walden ◽  
Xiao Kun Wang ◽  
James A. Cooper
Keyword(s):  
High Voltage ◽  
Current Density ◽  
Drift Region ◽  
Power Devices ◽  
Power Switching ◽  
Design Considerations ◽  
Blocking Voltage ◽  
Switching Devices

We compare the on-state characteristics of five 4H-SiC power devices designed to block 20 kV. At such a high blocking voltage, the on-state current density depends heavily on the degree of conductivity modulation in the drift region, making the IGBT and thyristor attractive devices for high blocking voltages.

4.5kV SiC JBS Diodes

2013 ◽  
Vol 347-350 ◽  
pp. 1506-1509 ◽  
Author(s):  
Yong Hong Tao ◽  
Run Hua Huang ◽  
Gang Chen ◽  
Song Bai ◽  
Yun Li
Keyword(s):  
Numerical Simulations ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Current Density ◽  
Doping Level ◽  
Doping Concentration ◽  
Device Structure ◽  
Reverse Voltage ◽  
Edge Termination ◽  
Drift Layer

High voltage 4H-SiC junction barrier schottky (JBS) diode with breakdown voltage higher than 4.5 kV has been fabricated. The doping level and thickness of the N-type drift layer and the device structure have been performed by numerical simulations. The thickness of the device epilayer is 50 μm, and the doping concentration is 1.2×1015 cm3. A floating guard rings edge termination has been used to improve the effectiveness of the edge termination technique. The diodes can block a reverse voltage of at least 4.5 kV, and the on-state current density was 80 A/cm2 at VF =4 V.

On-State and Switching Performance of High-Voltage 15 – 20 kV 4H-SiC DMOSFETs and IGBTs

2008 ◽  
Vol 600-603 ◽  
pp. 1143-1146 ◽  
Author(s):  
Tomohiro Tamaki ◽  
Ginger G. Walden ◽  
Yang Sui ◽  
James A. Cooper
Keyword(s):  
High Voltage ◽  
Current Density ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Total Power ◽  
Switching Frequency ◽  
Dimensional Parameter ◽  
Switching Performance ◽  
Blocking Voltage ◽  
Maximum Current

We compare the on-state and switching performance of high-voltage 4H-SiC n-channel DMOSFETs and p-channel IGBTs within a three-dimensional parameter space defined by blocking voltage, switching frequency, and current density. We determine the maximum current density each device can carry at a given switching frequency, such that the total power dissipation is 300 W/cm2. The IGBT current depends strongly on lifetime in the NPT buffer layer, and only weakly on lifetime in the drift layer. The MOSFET current is essentially independent of frequency.

950V, 8.7mohm-cm2 High Speed 4H-SiC Power DMOSFETs

2006 ◽  
Vol 911 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Charlotte Jonas ◽  
Bradley Heath ◽  
James Richmond ◽  
Anant Agarwal ◽  
...  
Keyword(s):  
Elevated Temperature ◽  
High Voltage ◽  
High Speed ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Blocking Voltage ◽  
Layer Resistance ◽  
High Speed Switching ◽  
Device Operation ◽  
Drift Layer

AbstractFabrication and characteristics of high voltage, high speed DMOSFETs in 4H-SiC are presented. The devices were built on 1.2×1016 cm-3 doped, 6 mm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 8.7 mW-cm2 and a blocking voltage of 950 V were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by 35% observed at 300oC, when compared to the value at room temperature. This is due to a negative shift in MOS threshold voltage, which decreases the MOS channel resistance at elevated temperatures. This effect cancels out the increase in drift layer resistance due to a decrease in bulk electron mobility at elevated temperature, resulting in a temperature stable on-resistance. The device operation at temperatures up to 300 oC and high speed switching results are also reported in this paper.

Development of Low RON,Diff, 12 kV, 4H-SiC GTOs For High-Power and High-Temperature Applications

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000149-000153 ◽  
Author(s):  
Lin Cheng ◽  
Anant K. Agarwal ◽  
Michael Oloughlin ◽  
Al Burk ◽  
Craig Capell ◽  
...  
Keyword(s):  
High Temperature ◽  
High Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
High Injection Level ◽  
Curve Tracer ◽  
Blocking Voltage ◽  
High Temperature Measurement ◽  
Forward Voltage Drop ◽  
Set Up

In this paper, we report our recently developed 1 × 1 cm2, 12 kV SiC GTOs with a very low differential on-resistance (RON,Diff) of 4 mΩ·cm2 with respect to the device active area at high injection level current of 100 A/cm2 or higher, which is more than a 40% reduction from our previously reported work. This significant reduction in the on-resistance was attributed to an improvement of carrier lifetime in the SiC bulk region. The SiC GTO was wire-bonded and attached to a high-voltage package before the high-temperature measurement. Forward characteristics of the device were then measured using a Tektronics 371 curve tracer from room temperature up to 400°C. Over the temperature range, the RON,Diff of the 4H-SiC GTO increased modestly from 4 mΩ·cm2 at 20°C to 4.7 mΩ·cm2 at 400°C, while the forward voltage drop at 100 A decreased slightly from 3.97 V at 20°C to 3.6 V at 400°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current was measured 0.66 μA at a VGK of 12 kV at 20°C.

New High-Voltage Unipolar Mode p+ Si/n– 4H-SiC Heterojunction Diode

2005 ◽  
Vol 483-485 ◽  
pp. 953-956 ◽  
Author(s):  
Tetsuya Hayashi ◽  
Hideaki Tanaka ◽  
Yoshio Shimoida ◽  
Satoshi Tanimoto ◽  
Masakatsu Hoshi
Keyword(s):  
Leakage Current ◽  
High Voltage ◽  
Drift Region ◽  
Heterojunction Diode ◽  
Inductive Load ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Blocking Voltage ◽  
Switching Characteristics ◽  
P Type

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.

scholarly journals Point Normal Metal-Superconductor (NS) Contact in Nonballistic Regime

2003 ◽  
Vol 17 (10n12) ◽  
pp. 649-656 ◽  
Author(s):  
I. N. Askerzade ◽  
I. O. Kulik
Keyword(s):  
Current Density ◽  
Andreev Reflection ◽  
Injection Current ◽  
Normal Metal ◽  
Excess Current ◽  
High Injection ◽  
Contact Conductivity ◽  
Injection Current Density

We analyze the point NS contact conductivity taking into account the depression of superconductivity at high-injection current density and Andreev reflection at the adaptive NS boundary. The dependence of the excess current on the voltage, as well as conductivity of contact at arbitrary voltage is obtained.

Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET

2013 ◽  
Vol 347-350 ◽  
pp. 1641-1645
Author(s):  
Run Hua Huang ◽  
Gang Chen ◽  
Song Bai ◽  
Rui Li ◽  
Yun Li ◽  
...  
Keyword(s):  
High Voltage ◽  
Current Density ◽  
Drain Current ◽  
Gate Bias ◽  
Edge Termination ◽  
Blocking Voltage ◽  
Drain Bias ◽  
Fabrication And Characterization ◽  
A Current

Simulation, Fabrication and characteristics of high voltage, normally-off JFETs in 4H-SiC are presented. The devices were built on ND= 1.01015 cm-3 doped 50μm thick n-type epilayer grown on a n+ 4H-SiC. Parameters of edge termination have been optimized by simulations. Its blocking voltage exceeds 4500V at gate bias VG = -6V and forward drain current is in excess of 3A at gate bias VG = 3V and drain bias VD = 5V corresponding a current density of 80A/cm2.

Development of SiC Super-Junction (SJ) Device by Deep Trench-Filling Epitaxial Growth

2013 ◽  
Vol 740-742 ◽  
pp. 785-788 ◽  
Author(s):  
Ryoji Kosugi ◽  
Yuuki Sakuma ◽  
Kazutoshi Kojima ◽  
Sachiko Itoh ◽  
Akiyo Nagata ◽  
...  
Keyword(s):  
Side Wall ◽  
Doping Profile ◽  
Total Charge ◽  
Concentration Region ◽  
Deep Trench ◽  
Blocking Voltage ◽  
Type Test ◽  
P Type ◽  
Drift Layer ◽  
The Ideal

We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.

Sign in / Sign up

Export Citation Format

Share Document