Development of SiC Super-Junction (SJ) Device by Deep Trench-Filling Epitaxial Growth

2013 ◽  
Vol 740-742 ◽  
pp. 785-788 ◽  
Author(s):  
Ryoji Kosugi ◽  
Yuuki Sakuma ◽  
Kazutoshi Kojima ◽  
Sachiko Itoh ◽  
Akiyo Nagata ◽  
...  
Keyword(s):  
Side Wall ◽  
Doping Profile ◽  
Total Charge ◽  
Concentration Region ◽  
Deep Trench ◽  
Blocking Voltage ◽  
Type Test ◽  
P Type ◽  
Drift Layer ◽  
The Ideal

We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.

15 kV, Large Area (1 cm2), 4H-SiC p-Type Gate Turn-Off Thyristors

2013 ◽  
Vol 740-742 ◽  
pp. 978-981 ◽  
Author(s):  
Lin Cheng ◽  
Anant K. Agarwal ◽  
Craig Capell ◽  
Michael J. O'Loughlin ◽  
Khiem Lam ◽  
...  
Keyword(s):  
High Voltage ◽  
Current Density ◽  
Large Area ◽  
Test Set ◽  
High Injection ◽  
Blocking Voltage ◽  
Set Up ◽  
P Type ◽  
Drift Layer ◽  
Injection Current Density

In this paper, we report our recently developed 1 cm2, 15 kV SiC p-GTO with an extremely low differential on-resistance (RON,diff) of 4.08 mΩ•cm2 at a high injection-current density (JAK) of 600 ~ 710 A/cm2. The 15 kV SiC p-GTO was built on a 120 μm, 2×1014/cm3 doped p-type SiC drift layer with a device active area of 0.521 cm2. Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the RON,diff at JAK of 600 ~ 710 A/cm2 decreased from 4.08 mΩ•cm2 at 20°C to 3.45 mΩ•cm2 at JAK of 600 ~ 680 A/cm2 at 200°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current at a VGK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

12 kV 4H-SiC p-IGBTs with Record Low Specific On-Resistance

2008 ◽  
Vol 600-603 ◽  
pp. 1187-1190 ◽  
Author(s):  
Q. Jon Zhang ◽  
Charlotte Jonas ◽  
Joseph J. Sumakeris ◽  
Anant K. Agarwal ◽  
John W. Palmour
Keyword(s):  
Carrier Lifetime ◽  
Drift Region ◽  
Gate Bias ◽  
Enhancement Layer ◽  
Channel Mobility ◽  
Dc Characteristics ◽  
Blocking Voltage ◽  
High Carrier ◽  
P Type ◽  
First Time

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

Fabrication of a P-Channel SiC-IGBT with High Channel Mobility

2013 ◽  
Vol 740-742 ◽  
pp. 958-961 ◽  
Author(s):  
Shuji Katakami ◽  
Hiroyuki Fujisawa ◽  
Kensuke Takenaka ◽  
Hitoshi Ishimori ◽  
Shinji Takasu ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Leakage Current Density ◽  
Current Density ◽  
Field Effect ◽  
Oxidation Process ◽  
Doping Profile ◽  
Base Layer ◽  
Channel Mobility ◽  
Insulated Gate Bipolar Transistor ◽  
Blocking Voltage

We fabricated and characterized an ultrahigh voltage (>10kV) p-channel silicon carbide insulated gate bipolar transistor (SiC-IGBT) with high channel mobility. Higher field-effect channel mobility of 13.5 cm2/Vs was achieved by the combination of adopting an n-type base layer with a retrograde doping profile and additional wet re-oxidation annealing (wet-ROA) at 1100°C in the gate oxidation process. The on-state characteristics of the p-channel SiC-IGBT at 200°C showed the low differential specific on-resistance of 24 mΩcm2 at VG = -20 V. The forward blocking voltage of the p-channel SiC-IGBT at 25°C was 10.2 kV a the leakage current density of 1.0 μA/cm2.

Quantum-Confined Optical Interband Transitions in 5-Doped Doping Superlattices

1989 ◽  
Vol 145 ◽  
Author(s):  
E. F. Schubert ◽  
T. D. Harris ◽  
J. E. Cunningham
Keyword(s):  
Emission Spectra ◽  
Doping Profile ◽  
Luminescence Spectra ◽  
Interband Transitions ◽  
Doping Technique ◽  
Quantum Confined ◽  
P Type ◽  
First Time ◽  
Experimental Absorption ◽  
Good Agreement

AbstractOptical absorption and photoluminescence experiments are performed on GaAs doping superlattices, which have a δ-function-like doping profile of alternating n-type and p-type dopant sheets. Absorption and emission spectra reveal for the first time the clear signature of quantum-confined interband transitions. The peaks of the experimental absorption and luminescence spectra are assigned to calculated energies of quantum-confined transitions with very good agreement. It is shown that the employment of the δ-doping technique results in improved optical properties of doping superlattices.

20 kV 4H-SiC N-IGBTs

2014 ◽  
Vol 778-780 ◽  
pp. 1030-1033 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
Michael J. O'Loughlin ◽  
Jack Clayton ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Leakage Current ◽  
Supply Voltage ◽  
Boost Converter ◽  
Power Switching ◽  
Switching Device ◽  
Blocking Voltage ◽  
Off Time ◽  
Drift Layer ◽  
Stop Buffer

A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

NOVEL ELECTRON GAS SYSTEMS

1999 ◽  
Vol 13 (05n06) ◽  
pp. 479-488 ◽  
Author(s):  
GAETANO SENATORE ◽  
F. RAPISARDA ◽  
S. CONTI
Keyword(s):  
Phase Diagram ◽  
Quantum Wells ◽  
Recent Progress ◽  
Electron Gas ◽  
Total Charge ◽  
Diffusion Monte Carlo ◽  
Electron Hole ◽  
Coupled Quantum Wells ◽  
Hartree Fock ◽  
The Ideal

We review recent progress on the physics of electrons in the bilayered electron gas, relevant to coupled quantum wells in GaAs/AlGaAs heterostructures. First, we focus on the phase diagram of a symmetric bilayer at T=B=0, obtained by diffusion Monte Carlo simulations. It is found that inter–layer correlations stabilize crystalline structures at intermediate inter–layer separation, while favouring a liquid phase at smaller distance. Also, the available DMC evidence is in contrast with the recently (Hartree–Fock) predicted total charge transfer (TCT), whereby all the electron spontaneously jump in one layer. In fact, one can show that such a TCT state is never stable in the ideal bilayer with no tunneling. We finally comment on ongoing DMC investigations on the electron-hole bilayer, where excitonic condensation is expected to take place.

Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance

2018 ◽  
Vol 924 ◽  
pp. 563-567
Author(s):  
Md Monzurul Alam ◽  
Dallas T. Morisette ◽  
James A. Cooper
Keyword(s):  
Drift Region ◽  
Charge Balance ◽  
Ideal Case ◽  
Charge Imbalance ◽  
Blocking Voltage ◽  
Practical Design ◽  
Proper Design ◽  
Improved Performance ◽  
The Relationship ◽  
The Ideal

In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance Ron,sp and blocking voltage VBR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

scholarly journals Investigation of Barrier Inhomogeneities and Electronic Transport on Al-Foil/p-Type-4H-SiC Schottky Barrier Diodes Using Diffusion Welding

Crystals ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 636
Author(s):  
Mehadi Hasan Ziko ◽  
Ants Koel ◽  
Toomas Rang ◽  
Muhammad Haroon Rashid
Keyword(s):  
Schottky Barrier ◽  
Barrier Height ◽  
Ideality Factor ◽  
Doping Profile ◽  
Structural Defects ◽  
Diffusion Welding ◽  
Native Oxide Layer ◽  
Electrical Characteristics ◽  
Discrete Energy Level ◽  
P Type

The diffusion welding (DW) is a comprehensive mechanism that can be extensively used to develop silicon carbide (SiC) Schottky rectifiers as a cheaper alternative to existing mainstream contact forming technologies. In this work, the Schottky barrier diode (SBD) fabricated by depositing Al-Foil on the p-type 4H-SiC substrate with a novel technology; DW. The electrical properties of physically fabricated Al-Foil/4H-SiC SBD have been investigated. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics based on the thermionic emission model in the temperature range (300 K–450 K) are investigated. It has been found that the ideality factor and barrier heights of identically manufactured Al-Foil/p-type-4H-SiC SBDs showing distinct deviation in their electrical characteristics. An improvement in the ideality factor of Al-Foil/p-type-4H-SiC SBD has been noticed with an increase in temperature. An increase in barrier height in fabricated SBD is also observed with an increase in temperature. We also found that these increases in barrier height, improve ideality factors and abnormalities in their electrical characteristics are due to structural defects initiation, discrete energy level formation, interfacial native oxide layer formation, inhomogenous doping profile distribution and tunneling current formation at the SiC sufaces.

scholarly journals Device Design Assessment of GaN Merged P-i-N Schottky Diodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1550 ◽  
Author(s):  
Yuliang Zhang ◽  
Xing Lu ◽  
Xinbo Zou
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
Background Concentration ◽  
Model Parameters ◽  
Design Assessment ◽  
Blocking Voltage ◽  
Aided Design ◽  
Drift Layer

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study their influence on the device’s performance. Extending the inter-p-GaN region distance or the Schottky contact portion could enhance the forward conduction capability; however, this leads to compromised electrical field screening effects from neighboring PN junctions, as well as reduced breakdown voltage. By reducing the drift layer background concentration, a higher breakdown voltage was expected for MPSs, as a larger portion of the drift layer itself could be depleted for sustaining vertical reverse voltage. However, lowering the drift layer concentration would also result in a reduction in forward conduction capability. The method and results of this study provide a guideline for designing MPS diodes with target blocking voltage and forward conduction at a low bias.

CIMOSFET: A New MOSFET on SiC with a Superior Ron·Qgd Figure of Merit

2015 ◽  
Vol 821-823 ◽  
pp. 765-768 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Jennifer Duc ◽  
Brett Hull ◽  
Jonathan Young ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
Figure Of Merit ◽  
Oxide Interface ◽  
Inductive Load ◽  
Switching Performance ◽  
Fast Switching ◽  
Drain Bias ◽  
C 30 ◽  
P Type ◽  
Drift Layer

A new MOSFET structure named the CIMOSFET (Central Implant MOSFET) has been presented and experimentally confirmed on SiC. The novelty of the CIMOSFET lies in a p-type implant introduced in the middle of the JFET area to shield the oxide interface field from the drain bias. Compared to the commercially available 1200 V SiC DMOSFET, this new concept has significantly reduced the on-resistance (Ron) and gate-drain capacitance (Cgd) simultaneously, produced a record low Ron·Qgd Figure of Merit of 455 mΩ·nC at 25°C, and 700 mΩ·nC at 150°C (~30% of the best data found). Only a 55% increase in Ron from 25°C to 150°C has been achieved due to the highly doped drift layer used on the CIMOSFET. Inductive load switching measurements have shown the CIMOSFET exhibits a fast switching performance. The CIMOSFET blocks 1600 V even though its drift doping is higher than that of the conventional DMOSFETs.

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