scholarly journals Fabrication of Multiscale-Structure Wafer-Level Microlens Array Mold

2019 ◽  
Vol 9 (3) ◽  
pp. 487 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Xiaoxiao Wei
Keyword(s):  
Low Cost ◽  
Form Factors ◽  
Cost Effective ◽  
Microlens Array ◽  
Practical Method ◽  
Reduced Form ◽  
Wafer Level ◽  
Polycrystalline Aluminum ◽  
Microlens Arrays ◽  
Multiscale Structure

The design and manufacture of cost-effective miniaturized optics at wafer level, usingadvanced semiconductor-like techniques, enables the production of reduced form-factor cameramodules for optical devices. However, suppressing the Fresnel reflection of wafer-level microlensesis a major challenge. Moth-eye nanostructures not only satisfy the antireflection requirementof microlens arrays, but also overcome the problem of coating fracture. This novel fabricationprocess, based on a precision wafer-level microlens array mold, is designed to meet the demandfor small form factors, high resolution, and cost effectiveness. In this study, three different kinds ofaluminum material, namely 6061-T6 aluminum alloy, high-purity polycrystalline aluminum, and purenanocrystalline aluminum were used to fabricate microlens array molds with uniform nanostructures.Of these three materials, the pure nanocrystalline aluminum microlens array mold exhibited auniform nanostructure and met the optical requirements. This study lays a solid foundation for theindustrial acceptation of novel and functional multiscale-structure wafer-level microlens arrays andprovides a practical method for the low-cost manufacture of large, high-quality wafer-level molds.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

The Production of Reduced Graphene Oxide by a Low-Cost Vacuum System for Supercapacitor Applications

2018 ◽  
Vol 930 ◽  
pp. 609-612
Author(s):  
Quezia Cardoso ◽  
Franks Martins Silva ◽  
Ligia Silverio Vieira ◽  
Julio Cesar Serafim Casini ◽  
Solange Kazume Sakata ◽  
...  
Keyword(s):  
Graphene Oxide ◽  
Large Scale ◽  
Low Cost ◽  
High Vacuum ◽  
Cost Effective ◽  
Practical Method ◽  
Raw Material ◽  
Vacuum System ◽  
X Ray ◽  
Pump Pressure

Graphene has attracted significant interest because of its excellent electrical properties. However, a practical method for producing graphene on a large scale is yet to be developed. Graphene oxide (GO) can be partially reduced to graphene-like sheets by removing the oxygen-containing groups and recovering the conjugated structure. GO can be produced using inexpensive graphite as the raw material via cost-effective chemical methods. High vacuum and temperature (10−7 mbar and 1100°C, respectively) conditions are well-known to enable the preparation of reduced powder at the laboratory scale. However, a large-scale high vacuum reduction system that can be routinely operated at 10−7 mbar requires considerable initial capital as well as substantial operational and maintenance costs. The current study aims at developing an inexpensive method for the large-scale reduction of graphene oxide. A stainless steel vessel was evacuated to backing-pump pressure (10−2 mbar) and used to process GO at a range of temperatures. The reduction of GO powder at low vacuum pressures was attempted and investigated by X-ray diffraction and Fourier transform infrared spectroscopy. The experimental results of processing GO powder at various temperatures (200–1000°C) at relatively low pressures are reported. The microstructures of the processed materials were investigated using scanning electron microscopy and chemical microanalyses via energy dispersive X-ray analysis.

Ethanol Induced Shape Recovery and Swelling in Poly(methyl methacrylate) and Applications in Fabrication of Microlens Array

2012 ◽  
Vol 77 ◽  
pp. 354-358 ◽  
Author(s):  
Yong Zhao ◽  
Chang Chun Wang ◽  
Wei Min Huang ◽  
Hendra Purnawali
Keyword(s):  
Methyl Methacrylate ◽  
Shape Recovery ◽  
Cost Effective ◽  
Microlens Array ◽  
Surface Patterning ◽  
The Other ◽  
Molecular Relaxation ◽  
Microlens Arrays ◽  
Poly Methyl Methacrylate ◽  
Effective Manner

The transportation phenomenon of ethanol in pre-deformed poly(methyl methacrylate) (PMMA) is systematically investigated. Two different phenomena simultaneously occur during this process. One is shape recovery, which is resulted from the ethanol induced softening and plasticization of PMMA. The other is swelling, which is produced by the ethanol induced molecular relaxation. Based on this study, a novel surface patterning method is proposed to fabricate PMMA microlens arrays in a simple and cost-effective manner.

Rectangular Microlens Array Having High Sag for Multi Chip LED Packaging

2006 ◽  
Vol 326-328 ◽  
pp. 1491-1494 ◽  
Author(s):  
Won Kyu Jeung ◽  
Chang Hyun Lim ◽  
Tae Hoon Kim ◽  
Seog Moon Choi
Keyword(s):  
Mass Production ◽  
Light Emitting Diode ◽  
Low Cost ◽  
Large Diameter ◽  
Optical Loss ◽  
Microlens Array ◽  
Wafer Level ◽  
Rectangular Shape ◽  
Replication Method ◽  
Optical Extraction

A novel rectangular shape microlens array having high sag for solid-state lighting is presented. The rectangular shape of proposed microlens can maximize the fill factor of silicon based light-emitting-diode (LED) packaging and minimize the optical loss through the reduction of unnecessary reflection at the same time. Microlens, which has high sag, over 3 75 μm and large diameter, over 3 mm can enormously enhance output optical extraction eff iciency. Moreover wafer level packaging technology is adopted to improve the aligning accu racy and mass production of LED packaging. This wafer level microlens array can be direc tly fabricated on LED packaging using replication method. It has many advantages in optica l properties, low cost, high aligning accuracy, and mass production.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

Thin Film Packaging Reinforcement for Overmolded MEMS

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001095-001119
Author(s):  
Gillot Charlotte ◽  
Jean-Louis Pornin ◽  
Christophe Billard ◽  
Emannuelle Lagoute ◽  
Mihel Pellat ◽  
...  
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Low Cost ◽  
Short Circuit ◽  
Cost Effective ◽  
Wafer Level ◽  
Silicon Area ◽  
Mechanical Constraints ◽  
Test Card ◽  
Manufacturing Technologies

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded. The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints. Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.

scholarly journals Noncontact Microembossing Technology for Fabricating Thermoplastic Optical Polymer Microlens Array Sheets

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Xuefeng Chang ◽  
Dan Xie ◽  
Xiaohong Ge ◽  
Hui Li
Keyword(s):  
Mechanical Characteristics ◽  
Optical Glass ◽  
Low Cost ◽  
Microlens Array ◽  
Production Costs ◽  
Efficient Production ◽  
Promising Technique ◽  
Element Analysis ◽  
Microlens Arrays ◽  
Optical Polymer

Thermoplastic optical polymers have replaced traditional optical glass for many applications, due to their superior optical performance, mechanical characteristics, low cost, and efficient production process. This paper investigates noncontact microembossing technology used for producing microlens arrays made out of PMMA (polymethyl methacrylate), PS (polyStyrene), and PC (polycarbonate) from a quartz mold, with microhole arrays. An array of planoconvex microlenses are formed because of surface tension caused by applying pressure to the edge of a hole at a certain glass transition temperature. We studied the principle of noncontact microembossing techniques using finite element analysis, in addition to the thermal and mechanical properties of the three polymers. Then, the independently developed hot-embossing equipment was used to fabricate microlens arrays on PMMA, PS, and PC sheets. This is a promising technique for fabricating diverse thermoplastic optical polymer microlens array sheets, with a simple technological process and low production costs.

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