Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

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Suppression of Short Channel Effects in Ferroelectric Si Junctionless Transistors with 8 nm Gate Length Defined by Helium Ion Beam Lithography

Journal of Materials Chemistry C ◽

10.1039/d1tc00431j ◽

2021 ◽

Author(s):

Teng Jan Chang ◽

Ting-Yun Wang ◽

Chin-I Wang ◽

Zheng-da Huang ◽

Yu-Sen Jiang ◽

...

Keyword(s):

Gate Dielectric ◽

Ion Beam ◽

Gate Length ◽

Short Channel Effects ◽

Short Channel ◽

Ion Beam Lithography ◽

Helium Ion ◽

Channel Effects ◽

Junctionless Transistors ◽

First Time

Performance enhancements of Si junctionless transistors (JLTs) with a short gate length (LG) of only ~8 nm by a pronounced ferroelectric (FE) gate dielectric are demonstrated for the first time....

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The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension

MRS Proceedings ◽

10.1557/proc-0912-c01-06 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 7

Author(s):

Bartek Pawlak ◽

Ray Duffy ◽

Emmanuel Augendre ◽

Simone Severi ◽

Tom Janssens ◽

...

Keyword(s):

Rapid Thermal Annealing ◽

Successful Implementation ◽

Gate Length ◽

Short Channel Effects ◽

Mos Transistors ◽

Short Channel ◽

Mos Devices ◽

Channel Effects ◽

20 Nm ◽

The Impact

AbstractAs extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.

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Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

MRS Proceedings ◽

10.1557/proc-716-b3.3 ◽

2002 ◽

Vol 716 ◽

Author(s):

Nihar R. Mohapatra ◽

Madhav P. Desai ◽

Siva G. Narendra ◽

V. Ramgopal Rao

Keyword(s):

Gate Dielectric ◽

Gate Dielectrics ◽

Channel Length ◽

Mos Transistors ◽

Short Channel ◽

Technology Scaling ◽

Mos Transistor ◽

Wide Range ◽

Impact Of Technology ◽

The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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A New Approach to the Characteristics and Short-Channel Effects of Double-Gate Carbon Nanotube Field-Effect Transistors using MATLAB: A Numerical Study

Zeitschrift für Naturforschung A ◽

10.5560/zna.2012-0024 ◽

2012 ◽

Vol 67 (6-7) ◽

pp. 317-326 ◽

Cited By ~ 1

Author(s):

Alireza Heidari ◽

Niloofar Heidari ◽

Foad Khademi Jahromi ◽

Roozbeh Amiri ◽

Mohammadali Ghorbani

Keyword(s):

Carbon Nanotube ◽

Field Effect ◽

Field Effect Transistors ◽

Open Boundary ◽

Double Gate ◽

Short Channel Effects ◽

Drain Voltage ◽

Short Channel ◽

Channel Effects ◽

The Impact

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

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CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156406003618 ◽

2006 ◽

Vol 16 (01) ◽

pp. 193-219 ◽

Cited By ~ 1

Author(s):

S. DELEONIBUS ◽

B. de SALVO ◽

T. ERNST ◽

O. FAYNOT ◽

T. POIROUX ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Gate Dielectric ◽

Low Voltage ◽

Short Channel Effects ◽

Short Channel ◽

Trade Offs ◽

Future System ◽

The Future ◽

Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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Effect of organic gate dielectric material properties on interfacial charging and discharging of pentacene MIM device

Physics Procedia ◽

10.1016/j.phpro.2011.05.014 ◽

2011 ◽

Vol 14 ◽

pp. 62-66 ◽

Cited By ~ 1

Author(s):

Kateryna Bazaka ◽

Mohan V. Jacob ◽

Dai Taguchi ◽

Takaaki Manaka ◽

Mitsumasa Iwamoto

Keyword(s):

Material Properties ◽

Gate Dielectric ◽

Dielectric Material ◽

Gate Dielectric Material

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Short gate length AlGaN/GaN HEMTs

MRS Proceedings ◽

10.1557/proc-622-t6.29.1 ◽

2000 ◽

Vol 622 ◽

Author(s):

O. Breitschädel ◽

L. Kley ◽

H. Gräbeldinger ◽

B. Kuhn ◽

F. Scholz ◽

...

Keyword(s):

High Frequency ◽

Device Performance ◽

Gate Length ◽

Short Channel Effects ◽

Short Channel ◽

Channel Effects ◽

Gan Hemts ◽

Output Characteristics ◽

Frequency Behavior ◽

Nm Range

ABSTRACTWe report on our progress on the fabrication of AlGaN/GaN HEMTs with extremely short gate length. AlGaN/GaN HEMTs with different gate length from 6 νm down to 60nm were fabricated to investigate DC- and high frequency behavior as well as short channel effects. We have found that the transistors with gates in the 100 nm range can be improved in the device performance with respect to transconductance and high frequency but shows also short channel effects as the loss of saturation in the output characteristics and a strong dependency of the threshold voltage on the gate length.

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