A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

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A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

Journal of Circuits System and Computers ◽

10.1142/s021812660700385x ◽

2007 ◽

Vol 16 (04) ◽

pp. 627-639 ◽

Cited By ~ 4

Author(s):

VARAKORN KASEMSUWAN ◽

WEERACHAI NAKHLO

Keyword(s):

Power Dissipation ◽

Harmonic Distortion ◽

Cmos Technology ◽

Current Conveyor ◽

Common Source ◽

Output Stage ◽

Circuit Performance ◽

Rail To Rail ◽

Source Follower ◽

Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

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High Frequency Unity Gain Buffer in 90-nm CMOS Technology

Journal of Circuits System and Computers ◽

10.1142/s0218126616500717 ◽

2016 ◽

Vol 25 (07) ◽

pp. 1650071

Author(s):

Shuo Li ◽

Xiaomeng Zhang ◽

Saiyu Ren

Keyword(s):

Harmonic Distortion ◽

Low Frequency ◽

Cmos Technology ◽

Common Source ◽

Active Load ◽

Cmos Design ◽

Saturation Region ◽

Unity Gain ◽

Unity Gain Buffer ◽

Voltage Swing

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

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Simple Current-Mode Squaring and Square-Rooting Circuits: Applications of MO-CCCCTA

Trends in Sciences ◽

10.48048/tis.2021.721 ◽

2021 ◽

Vol 18 (23) ◽

pp. 721

Author(s):

Suvajit Roy ◽

Tapas Kumar Paul ◽

Radha Raman Pal

Keyword(s):

Power Dissipation ◽

Current Mode ◽

Transfer Characteristic ◽

Cmos Process ◽

Temperature Drift ◽

Transconductance Amplifier ◽

Static Power ◽

Linearity Error ◽

Design Ideas ◽

Characteristic Measurement

This work provides new designs of simple current-mode squaring and square-rooting circuits using multiple-output current controlled current conveyor transconductance amplifier (MO-CCCCTA) as an active building block. Since the proposed circuits need no other external components, they are capable of high-frequency operation and well fitted for IC fabrication. Furthermore, they are insensitive to ambient temperature and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA. Additionally, the effects of MO-CCCCTA non-idealities on the designed circuits have also been investigated and discussed. Simulation results generated through PSPICE software using TSMC 0.18 µm CMOS process parameters have been presented to justify the theoretical analysis. The static power consumption, bandwidth, and maximum linearity error in dc transfer characteristic measurement for the square-rooting circuit are found to be 0.17 mW, 445.63 MHz and 1.12 %, while for the squaring circuit they are 0.326 mW, 61.15 MHz and 2.38 %, respectively. The application of the reported circuits as a 2-input vector summation circuit has also been included to strengthen the design ideas. HIGHLIGHTS Simple structures of fully integrable current-mode squarers and square-rooters with low component count and lower power dissipation The circuits are insensitive to temperature drift and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA Bandwidth, static power dissipation, linearity error of square-rooter are 445.63 MHz, 0.17 mW & ≤ 1.12 %; and for the squarer 61.15 MHz, 0.326 mW & 2.38 %, respectively GRAPHICAL ABSTRACT

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Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

Journal of Circuits System and Computers ◽

10.1142/s0218126620500383 ◽

2019 ◽

Vol 29 (03) ◽

pp. 2050038

Author(s):

Mohammad Moradinezhad Maryan ◽

Seyed Javad Azhari ◽

Mehdi Ayat ◽

Reza Rezaei Siahrood

Keyword(s):

High Speed ◽

Harmonic Distortion ◽

Cmos Technology ◽

Monte Carlo Analysis ◽

Saturation Region ◽

Static Power ◽

Linearity Error ◽

Simulation Results ◽

Compact Design ◽

Four Quadrant

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

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To Design a Cascode LNA by Using Channel-Length-Split Device with Constant-gm in a 0.35 μm Silicon CMOS Technology

The Open Materials Science Journal ◽

10.2174/1874088x01610010079 ◽

2016 ◽

Vol 10 (1) ◽

pp. 79-88 ◽

Cited By ~ 1

Author(s):

Jui-Lin Lai ◽

Ting-You Lin ◽

Cheng-Fang Tai ◽

Rong-Jian Chen

Keyword(s):

Cmos Technology ◽

Channel Length ◽

Low Noise ◽

Output Stage ◽

Split Method ◽

Offset Voltage ◽

Rail To Rail ◽

In Series ◽

Compensation Technique ◽

Differential Pair

In the paper, the folded-cascode low-noise operational amplifier (LNA) with constant-gm is proposed and analyzed. The channel-length split technique adopted to expand ratio of W/L of the differential pair transistor to improve the performance of LNA for the gain bandwidth product, noise and offset voltage. The channel-length split method is separated differential input transistor into 2 transistors in series. The area of the transistor (W, L) can be properly increased to effectively decrease the flick noise. The double indirect-frequency compensation technique and the clamping circuit are adopted in amplifier to increase the bandwidth. The proposed two sets input differential pair can be provided a constant-gm value and rail-to-rail swing during the operating region. The floating-point structure is used to reach rail-to-rail swing at output stage. Simulation results show that the gain, constant-gm in input stag, noise, offset-voltage, PSRR, CMRR and ICMR of amplifier are improved. The characteristics of LNA are successfully verified by the TSMC 0.35um 2P4M CMOS technology. There have a great potential in the VLSI implementation used in the portable electronic and bio-medicine product applications.

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Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Circulation in Computer Science ◽

10.22632/ccs-2017-251-50 ◽

2017 ◽

Vol 2 (2) ◽

pp. 15-19 ◽

Cited By ~ 3

Author(s):

Md. Saud Al Faisal ◽

Md. Rokib Hasan ◽

Marwan Hossain ◽

Mohammad Saiful Islam

Keyword(s):

High Speed ◽

Field Effect Transistors ◽

Cmos Technology ◽

Channel Length ◽

Capacitive Coupling ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel ◽

Channel Effects ◽

Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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