Operation and performance of the ATLAS semiconductor tracker in LHC Run 2

The semiconductor tracker (SCT) is one of the tracking systems for charged particles in the ATLAS detector. It consists of 4088 silicon strip sensor modules. During Run 2 (2015–2018) the Large Hadron Collider delivered an integrated luminosity of 156 fb-1 to the ATLAS experiment at a centre-of-mass proton-proton collision energy of 13 TeV. The instantaneous luminosity and pile-up conditions were far in excess of those assumed in the original design of the SCT detector. Due to improvements to the data acquisition system, the SCT operated stably throughout Run 2. It was available for 99.9% of the integrated luminosity and achieved a data-quality efficiency of 99.85%. Detailed studies have been made of the leakage current in SCT modules and the evolution of the full depletion voltage, which are used to study the impact of radiation damage to the modules.

Method for noncontact measurement of 2DEG mobility and carrier density in AlGaN/GaN on semi-insulating wafers

We present a charge-assisted sheet resistance technique for noncontact wafer level determination of 2DEG mobility vs. sheet carrier density without any test structures or gates. Instead, the electrical biasing of 2DEG is provided by surface charge deposition, using a corona charging method. Analysis of the sheet resistance vs. deposited charge identifies the 2DEG full depletion condition and enables calculation of the 2DEG sheet carrier density required for the mobility. Results for AlGaN/GaN heterostructures on semi-insulating SiC and sapphire substrates show good agreement with Hall results at a zero-bias condition.

Radiation Hardness Property of Ultra-Fast 3D-Trench Electrode Silicon Detector on N-Type Substrate

The radiation fluence of high luminosity LHC (HL-LHC) is predicted up to 1 × 1016 1 MeV neq/cm2 in the ATLAS and CMS experiments for the pixel detectors at the innermost layers. The increased radiation leads to the degradation of the detector properties, such as increased leakage current and full depletion voltage, and reduced signals and charge collection efficiency, which means it is necessary to develop the radiation hard semiconductor devices for very high luminosity colliders. In our previous study about ultra-fast 3D-trench electrode silicon detectors, through induced transient current simulation with different minimum ionizing particle (MIP) hitting positions, the ultra-fast response times ranging from 30 ps to 140 ps were verified. In this work, the full depletion voltage, breakdown voltage, leakage current, capacitance, weighting field and MIP induced transient current (signal) of the detector after radiation at different fluences will be simulated and calculated with professional software, namely the finite-element Technology Computer-Aided Design (TCAD) software frameworks. From analysis of the simulation results, one can predict the performance of the detector in heavy radiation environment. The fabrication of pixel detectors will be carried out in CMOS process platform of IMECAS based on ultra-pure high resistivity (up to 104 ohm·cm) silicon material.

Design and Characterization of Backside Termination Structures for Thick Fully-Depleted MAPS

Fully Depleted Monolithic Active Pixel Sensors (FD-MAPS) represent an appealing alternative to hybrid detectors for radiation imaging applications. We have recently demonstrated the feasibility of FD-MAPS based on a commercial 110 nm CMOS technology, adapted using high-resistivity substrates and backside post-processing. A p/n junction diode, fabricated on the detector backside using low-temperature processing steps after the completion of the front-side Back End of Line (BEOL), is reverse-biased to achieve the full depletion of the substrate and thus fast charge collection by drift. Test diodes including termination structures with different numbers of floating guard rings and different pitches were fabricated together with other Process Control Monitor structures. In this paper, we present the design of the backside diodes, together with results from the electrical characterization of the test devices, aiming to improve understanding of the strengths and limitations of the proposed approach. Characterization results obtained on several wafers demonstrate the effectiveness of the termination rings in increasing the breakdown voltage of the backside diodes and in coping with the variability of the passivation layer characteristics. A breakdown voltage exceeding 400 V in the worst case was demonstrated in devices with 30 guard rings with 6 μm pitch, thus enabling the full depletion of high-resistivity substrates with a thickness larger than or equal to 300 μm. Additionally, we show the first direct comparison for this technology of measured pixel characteristics with 3D TCAD simulations, proving a good agreement in the extracted operating voltages.

Silicon Carbide Microstrip Radiation Detectors

Compared with the most commonly used silicon and germanium, which need to work at cryogenic or low temperatures to decrease their noise levels, wide-bandgap compound semiconductors such as silicon carbide allow the operation of radiation detectors at room temperature, with high performance, and without the use of any bulky and expensive cooling equipment. In this work, we investigated the electrical and spectroscopic performance of an innovative position-sensitive semiconductor radiation detector in epitaxial 4H-SiC. The full depletion of the epitaxial layer (124 µm, 5.2 × 1013 cm−3) was reached by biasing the detector up to 600 V. For comparison, two different microstrip detectors were fully characterized from −20 °C to +107 °C. The obtained results show that our prototype detector is suitable for high resolution X-ray spectroscopy with imaging capability in a wide range of operating temperatures.

Low value for the static background dielectric constant in epitaxial PZT thin films

Ferroelectrics are intensively studied materials due to their unique properties with high potential for applications. Despite all efforts devoted to obtain the values of ferroelectric material constants, the problem of the magnitude of static dielectric constant remains unsolved. In this article it is shown that the value of the static dielectric constant at zero electric field and with negligible contribution from the ferroelectric polarization (also called static background dielectric constant, or just background dielectric constant) can be very low (between 10 and 15), possibly converging towards the value in the optical domain. It is also found that the natural state of an ideal, mono-domain, epitaxial ferroelectric is that of full depletion with constant capacitance at voltages outside the switching domain. The findings are based on experimental results obtained from a new custom method designed to measure the capacitance-voltage characteristic in static conditions, as well from Rayleigh analysis. These results have important implications in future analysis of conduction mechanisms in ferroelectrics and theoretical modeling of ferroelectric-based devices.

A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal’s experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10−7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal’s experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.