A Precise Implementation of Random Access Time Measurement for Embedded SRAM

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

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Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

Journal of Circuits System and Computers ◽

10.1142/s0218126621501061 ◽

2020 ◽

pp. 2150106

Author(s):

Harekrishna Kumar ◽

V. K. Tomar

Keyword(s):

Power Dissipation ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Static Random Access Memory ◽

Access Time ◽

Access Memory ◽

Subthreshold Region ◽

Noise Margin ◽

Static Noise

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

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Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

MRS Advances ◽

10.1557/adv.2019.212 ◽

2019 ◽

Vol 4 (48) ◽

pp. 2577-2584

Author(s):

James N. Pan

Keyword(s):

Quantum Wells ◽

High Frequency ◽

Nonvolatile Memory ◽

High Speed ◽

Random Access ◽

Cost Effective ◽

Cmos Technology ◽

Access Time ◽

Cmos Process ◽

Atomic Force

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

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A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference ◽

10.1109/esscirc.2017.8094590 ◽

2017 ◽

Cited By ~ 3

Author(s):

M. Pasotti ◽

M. Carissimi ◽

C. Auricchio ◽

D. Brambilla ◽

E. Calvetti ◽

...

Keyword(s):

Random Access ◽

Access Time ◽

Smart Power

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A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

2011 IEEE International Solid-State Circuits Conference ◽

10.1109/isscc.2011.5746281 ◽

2011 ◽

Cited By ~ 82

Author(s):

Shyh-Shyuan Sheu ◽

Meng-Fan Chang ◽

Ku-Feng Lin ◽

Che-Wei Wu ◽

Yu-Sheng Chen ◽

...

Keyword(s):

Random Access ◽

Access Time ◽

Resistive Ram

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VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY

IIUM Engineering Journal ◽

10.31436/iiumej.v12i1.25 ◽

2011 ◽

Vol 12 (1) ◽

pp. 13-30 ◽

Cited By ~ 13

Author(s):

Aminul Islam ◽

Mohd. Hasan

Keyword(s):

Random Access ◽

Memory Cell ◽

Static Random Access Memory ◽

Access Time ◽

Access Memory ◽

Static Noise Margin ◽

Noise Margin ◽

Sram Cell ◽

Pvt Variations ◽

Static Noise

This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).

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