Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2577-2584
Author(s):  
James N. Pan
Keyword(s):  
Quantum Wells ◽  
High Frequency ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Cost Effective ◽  
Cmos Technology ◽  
Access Time ◽  
Cmos Process ◽  
Atomic Force

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

STT-RAM CELL DESIGN CONSIDERING MTJ ASYMMETRIC SWITCHING

SPIN ◽  
2012 ◽  
Vol 02 (03) ◽  
pp. 1240007 ◽  
Author(s):  
YAOJUN ZHANG ◽  
WUJIE WEN ◽  
YIRAN CHEN
Keyword(s):  
Nonvolatile Memory ◽  
Random Access ◽  
High Resistance State ◽  
Spin Transfer Torque ◽  
Access Time ◽  
Cmos Process ◽  
Cell Structures ◽  
Integration Density ◽  
Resistance State ◽  
The Asymmetry

As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, nonvolatility, and good CMOS process compatibility. In this paper, we address the asymmetry in the write operations of STT-RAM cells: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite direction. Some special design concerns, e.g., the data-dependent write reliability, are raised by this observation. We systematically analyze the root reasons for the asymmetric switching of MTJs, including the thermal-induced statistical MTJ magnetization process, the asymmetric biasing condition of NMOS transistors, and the device variations of both NMOS and MTJ. Their impacts on STT-RAM write operations were also investigated. At last, we explore the design spaces of different STT-RAM cell structures by considering the asymmetry of write operations.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

Mechanical, Thermal and Flow Dynamics Issues in Compound Semiconductor MOCVD Reactor Design

1994 ◽  
Vol 340 ◽  
Author(s):  
A.I. Gurary ◽  
G.S. Tompa ◽  
K. Moy ◽  
P. Zawadzki
Keyword(s):  
Quantum Wells ◽  
High Speed ◽  
Chemical Vapor ◽  
Cost Effective ◽  
Rotating Disk ◽  
Compound Semiconductor ◽  
Element Analysis ◽  
Long Wavelength ◽  
Mocvd Reactor ◽  
Reactor Geometry

ABSTRACTIn recent years Metalorganic Chemical Vapor Deposition (MOCVD) becomes a key epitaxial process for a variety of compound semiconductor devices such as: GaAs/AlGaAs lasers, HEMTs, LEDs, photocathodes, solar cells, and MESFETs; InP/InGaAsP long wavelength lasers and detectors; InP/InGaAs quantum wells and detectors, etc. Development of reliable, high throughput equipment is a major task in the implementation of MOCVD into cost-effective manufacturings. We have used Computational Fluid Dynamics (CFD) and Finite Element Analysis (FEA) software to model thermal, structural, and flow processes for the scaling of EMCORE vertical, high speed rotating disk reactor (RDR) to large dimensions (four 4″ wafers located on 12″ wafer carrier). Flow modeling was used to determine basic reactor geometry and the relation between process parameters such as total reactant flow, temperature, pressure, and rotation speed. Thermal and structural analysis was used to produce a uniform substrate temperature, avoid reactor overheating and decrease thermal stress. Flow and temperature distribution predicted by the modeling were found to be well correlated with experimental results.

scholarly journals A miniaturized, high frequency mechanical scanner for high speed atomic force microscope using suspension on dynamically determined points

2015 ◽  
Vol 86 (11) ◽  
pp. 113703 ◽  
Author(s):  
Rodolf Herfst ◽  
Bert Dekker ◽  
Gert Witvoet ◽  
Will Crowcombe ◽  
Dorus de Lange ◽  
...  
Keyword(s):  
Atomic Force Microscope ◽  
High Frequency ◽  
High Speed ◽  
Atomic Force

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

scholarly journals Challenges and Applications of Emerging Nonvolatile Memory Devices

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1029 ◽  
Author(s):  
Writam Banerjee
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
High Density ◽  
Memory Storage ◽  
Access Memory ◽  
Ultra Low Power

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

The Recent Progress of Research on Resistive Random Access Memory

2013 ◽  
Vol 685 ◽  
pp. 372-377 ◽  
Author(s):  
Wen Wen Qiu ◽  
Hong Deng ◽  
Mi Li ◽  
Min Wei ◽  
Xue Ran Deng ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Recent Progress ◽  
Simple Structure ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Low Power Consumption ◽  
Access Memory ◽  
New Type

Resistive random access memory (RRAM) has attracted comprehensive attention from academia and industry as a new-type of nonvolatile memory. This memory has many advantages, such as high-speed, low power consumption, simple structure, high-density integration, etc. Therefore, it has a strong potential to replace DRAM. This paper summarizes the recent progress of the studies on RRAM. Although the achievement obtained has been summarized, there is still a long way from the real application. We also discuss the principle and related properties of RRAM and forecast the preparation trends of RRAM

Time-Domain Readout of 1T–1C DRAM Cells

2017 ◽  
Vol 27 (01) ◽  
pp. 1850005 ◽  
Author(s):  
Sherif M. Sharroush
Keyword(s):  
Time Domain ◽  
Noise Analysis ◽  
Average Power ◽  
Random Access ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Access Time ◽  
Technology Scaling ◽  
Sense Amplifier ◽  
Power Delay Product

The conventional readout of one-transistor–one-capacitor dynamic random-access memories (1T–1C DRAMs) depends on using a sense amplifier to develop the bitline voltage and settle it to the voltage of the power supply, [Formula: see text], or to 0[Formula: see text]V depending on whether the stored data is “1” or “0,” respectively. However, using the sense amplifier makes the reading process sluggish. In this paper, a capacitive-voltage divider-based readout scheme is proposed. According to this scheme, the developed bitline voltage is converted into a pulse with a certain starting time. Specifically, this pulse appears at a later time in case of “0” storage than that if a “1” is stored, thus the proposed scheme is aptly called “time-domain readout.” The effects of parameter and component mismatches and technology scaling on the proposed scheme are investigated. The proposed scheme is analyzed quantitatively with a suggestion given to widen the time gap between the starting times of the pulses corresponding to the “0” and “1” states. The proposed scheme is verified by simulation adopting the 45 nm CMOS technology with [Formula: see text][Formula: see text]V. According to the simulation results, percentage savings of 68.8%, 56.8%, and 32% in the read-access time, the read-cycle time, and the average power-delay product, respectively, are shown. The proposed scheme requires approximately 40% extra area overhead for the reading circuitry. Also, a noise analysis is performed and it is found that the device noise does not affect the proposed scheme significantly.

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