Compact 3D USB dongle monopole antenna for mobile wireless communication bands

2014 ◽  
Vol 6 (6) ◽  
pp. 639-644 ◽  
Author(s):  
Dalia M. Elsheakh ◽  
Amr M.E. Safwat
Keyword(s):  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Universal Serial Bus ◽  
High Impedance ◽  
Unit Cells ◽  
Operating Bandwidth ◽  
Service Bands ◽  
Internal Antenna ◽  
Meander Line

Three-dimensional compact volume internal antenna for universal serial bus (USB) dongle that covers hexa operating bands is proposed in this paper. The volume of the proposed USB dongle is 15×20×4 mm3; it is based on two connected monopoles, one of them is semi-circular monopole ended by three unit cells of meander-line and the other is a bent monopole with four unit cells of high-impedance wire. The proposed antenna is realized on a printed circuit board to reduce the fabrication costs. The coupling between the antenna elements broadens the operating bandwidth, which includes most of the wireless commercial service bands, GSM850/GSM900/UMTS/GSM1800/GSM1900/WCDMA2100/802.11b/g/LTE2600 (824–2690 MHz) as well as 802.11a/n (5150–5825 MHz). The antenna's simulated and experimental results are in good agreement.

Three Dimensional Detection of the via in the PCB CT Image Using Morphology Operation

2015 ◽  
Vol 752-753 ◽  
pp. 1406-1412
Author(s):  
Lei Zeng ◽  
Jian Chen ◽  
Han Ning Li ◽  
Bin Yan ◽  
Yi Fu Xu ◽  
...  
Keyword(s):  
Nondestructive Testing ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Detection Algorithm ◽  
Circuit Board ◽  
Dimensional Structure ◽  
Three Dimension ◽  
Shape Information ◽  
Printed Circuit ◽  
Testing Technology

In modern industry, the nondestructive testing of printed circuit board (PCB) can prevent effectively the system failure and is becoming more and more important. As a vital part of the PCB, the via connects the devices, the components and the wires and plays a very important role for the connection of the circuits. With the development of testing technology, the nondestructive testing of the via extends from two dimension to three dimension in recent years. This paper proposes a three dimensional detection algorithm using morphology method to test the via. The proposed algorithm takes full advantage of the three dimensional structure and shape information of the via. We have used the proposed method to detect via from PCB images with different size and quality, and found the detection performances to be very encouraging.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

2013 ◽  
Vol 795 ◽  
pp. 603-610 ◽  
Author(s):  
Mohamed Mazlan ◽  
A. Rahim ◽  
M.A. Iqbal ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
W. Razak ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Three Dimensional ◽  
Circuit Board ◽  
Junction Temperature ◽  
Inlet Velocity ◽  
Chip Carrier ◽  
Flow Through ◽  
Package Density ◽  
Heat And Fluid Flow

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages during the Assembly Process

2014 ◽  
Vol 2014 (1) ◽  
pp. 000355-000360
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional numerical finite element model is capable to use geometric and material properties which are not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an X-ray diffraction method (Rocking-Curve-Technique) showing a good agreement of the calculated and measured curvature radius values.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages During the Assembly Process

2015 ◽  
Vol 12 (2) ◽  
pp. 80-85 ◽  
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional, numerical, finite element model is capable of using geometric and material properties not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an x-ray diffraction method (rocking-curve technique) showing a good agreement of the calculated and measured curvature radius values.

High quality factor fractal inductor with complementary split-ring array inclusion

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 215-219
Author(s):  
Akhendra Kumar Padavala ◽  
Narayana Kiran Akondi ◽  
Bheema Rao Nistala
Keyword(s):  
Quality Factor ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Integrated Circuit Design ◽  
Split Ring ◽  
Content Type ◽  
Practical Implications

Purpose This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface. Design/methodology/approach Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value. Findings The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally. Practical implications The proposed method was able to significantly decrease the noise with increase in the speed of radio frequency and sensor-integrated circuit design. Originality/value Fractal inductor is designed and simulated with and without EBG surfaces. The measurement of printed circuit board prototypes demonstrates that the inclusion of split-ring array as EBG surface increases the quality factor by 90 per cent over standard fractal inductor of the same dimensions with a small degradation in inductance value and is capable of operating up to 2.4 GHz frequency range.

scholarly journals Affordable Thin Lens Using Single Polarized Disparate Filter Arrays for Beyond 5G toward 6G

Sensors ◽  
2019 ◽  
Vol 19 (18) ◽  
pp. 3982
Author(s):  
Inseop Yoon ◽  
Seongwoog Oh ◽  
Jungsuek Oh
Keyword(s):  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Design Procedure ◽  
Circuit Board ◽  
Process Conditions ◽  
60 Ghz ◽  
Thin Lens ◽  
Gain Enhancement ◽  
Unit Cells ◽  
Pcb Manufacturing

This paper proposes a novel design approach for a thin lens with the aim of overcoming fineness limits in the commercial millimeter wave printed circuit board (PCB) manufacturing process. The PCB manufacturing process typically does not allow the fabrication of metallic patterns with a gap and width of less than 100 μm. This hampers expanding thin lens technology to 5G commercial applications, especially when such technology is considered for 60 GHz or higher frequency, which requires a finer gap and width of metallic traces. This paper proposes that problematic process conditions can be mitigated when a lens is designed by establishing single-polarized lumped element models where larger capacitance and inductance values can be obtained for the same patch and grid unit cells. While the proposed design technique is more advantageous at higher target frequencies, a 60 GHz application and a wireless backhaul system is selected because of a limited range of frequencies that can be measured by an available vector network analyzer. The required gap or width of metallic traces can be widened significantly by using the proposed single-polarized unit cells to acquire the same in-plane capacitance or inductance. This enables the lens operating at higher-frequency under the process limits in fabricable fine traces. Finally, the effectiveness of the simulated design procedure is demonstrated by fabricating a 60 GHz thin lens that can achieve a gain enhancement of 16 dB for a 4 × 4 patch antenna array with a gain of 16.5 dBi.

Thermal Performance of Microelectronic Substrates With Submillimeter Integrated Vapor Chamber

2019 ◽  
Vol 141 (5) ◽  
Author(s):  
Sangbeom Cho ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Thermal Performance ◽  
Printed Circuit Board ◽  
Mechanical Design ◽  
Three Dimensional ◽  
Circuit Board ◽  
Working Fluid ◽  
Vapor Chamber ◽  
Conduction Model ◽  
Printed Circuit

We develop a vapor chamber integrated with a microelectronic packaging substrate and characterize its heat transfer performance. A prototype of vapor chamber integrated printed circuit board (PCB) is fabricated through successful completion of the following tasks: patterning copper micropillar wick structures on PCB, mechanical design and fabrication of condenser, device sealing, and device vacuuming and charging with working fluid. Two prototype vapor chambers with distinct micropillar array designs are fabricated, and their thermal performance tested under various heat inputs supplied from a 2 mm × 2 mm heat source. Thermal performance of the device improves with heat inputs, with the maximum performance of ∼20% over copper plated PCB with the same thickness. A three-dimensional computational fluid dynamics/heat transfer (CFD/HT) numerical model of the vapor chamber, coupled with the conduction model of the packaging substrate is developed, and the results are compared with test data.

Development of a Fused Deposition Modeling System for Low Melting Temperature Metal Alloys

2013 ◽  
Vol 135 (1) ◽  
Author(s):  
Jorge Mireles ◽  
Ho-Chan Kim ◽  
In Hwan Lee ◽  
David Espalin ◽  
Francisco Medina ◽  
...  
Keyword(s):  
Melting Temperature ◽  
Fused Deposition Modeling ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Single Layer ◽  
Metal Alloys ◽  
Circuit Board ◽  
Fused Deposition ◽  
Extrusion Head ◽  
Deposition Modeling

This research focused on extending the applications of fused deposition modeling (FDM) by extrusion and deposition of low melting temperature metal alloys to create three-dimensional metal structures and single-layer contacts which may prove useful for electronic interconnects. Six commercially available low melting temperature solder alloys (Bi36Pb32Sn31Ag1, Bi58Sn42, Sn63Pb37, Sn50Pb50, Sn60Bi40, Sn96.5Ag3.5) were tested for the creation of a fused deposition modeling for metals (FDMm) system with special attention given to Sn–Bi solders. An existing FDM 3000 was used and two alloys were successfully extruded through the system's extrusion head. Deposition was achieved through specific modifications to system toolpath commands and a comparison of solders with eutectic and non-eutectic compositions is discussed. The modifications demonstrate the ability to extrude simple single-layer solder lines with varying thicknesses, including sharp 90 deg angles and smooth curved lines and showing the possibility of using this system for printed circuit board applications in which various connections need to be processed. Deposition parameters altered for extrusion and the deposition results of low melting temperature metal alloys are introduced.

Utilization of Waste Printed Circuit Board Resin in Controlled Low-Strength Materials

2013 ◽  
Vol 699 ◽  
pp. 630-636 ◽  
Author(s):  
Ing Jia Chiou ◽  
Chu Chan Chiang ◽  
Cheng Lan Ho
Keyword(s):  
Printed Circuit Board ◽  
Setting Time ◽  
Circuit Board ◽  
Fine Aggregate ◽  
Compacted Clay ◽  
Printed Circuit ◽  
Waste Printed Circuit Board ◽  
High Impedance ◽  
Slump Flow ◽  
Low Strength

In this investigation, waste printed circuit board resin powder (WPCBRP) was used to replace 0-30% of the fine aggregate in controlled low-strength materials (CLSM), to explore their rheological behavior, mechanical behavior, and durability. The results thus obtained demonstrate that when 10% of the fine aggregate was replaced by WPCBRP, the adjusted slump flow, setting time, and compressive strength could all met the standards at the ages of 12 hours and 28 days, with a high impedance of 1.54-1.63 kΩcm. CLSM with WPCBRP has a similar water permeability, of between 10-8 and 10-9 cm/s, to that of compacted clay. Therefore, this form of CLSM is impervious, and has a lower compacted settlement when compared with clay.

scholarly journals Ka-Band Slot-Microstrip-Covered and Waveguide-Cavity-Backed Monopulse Antenna Array

2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Li-Ming Si ◽  
Yong Liu ◽  
Yongjun Huang ◽  
Weiren Zhu
Keyword(s):  
Antenna Array ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Dielectric Substrate ◽  
Circuit Board ◽  
Slot Antenna ◽  
Ka Band ◽  
Operating Bandwidth ◽  
The Difference ◽  
Waveguide Slot Antenna

A slot-microstrip-covered and waveguide-cavity-backed monopulse antenna array is proposed for high-resolution tracking applications at Ka-band. The monopulse antenna array is designed with a microstrip with2×32slots, a waveguide cavity, and a waveguide monopulse comparator, to make the structure simple, reduce the feeding network loss, and increase the frequency bandwidth. The2×32slot-microstrip elements are formed by a metal clad dielectric substrate and slots etched in the metal using the standard printed circuit board (PCB) process with dimensions of 230 mm  ×  10 mm. The proposed monopulse antenna array not only maintains the advantages of the traditional waveguide slot antenna array, but also has the characteristics of wide bandwidth, high consistence, easy of fabrication, and low cost. From the measured results, it exhibits good monopulse characteristics, including the following: the maximum gains of sum pattern are greater than 24 dB, the 3 dB beamwidth of sum pattern is about 2.2 degrees, the sidelobe levels of the sum pattern are less than −18 dB, and the null depths of the difference pattern are less than −25 dB within the operating bandwidth between 33.65 GHz and 34.35 GHz for VSWR ≤ 2.

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