Active Strain Engineering of Soft Plasmene Nanosheets by Thermoresponsive Hydrogels

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

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Uniform Monolayer of Organic Molecules Provides Precise Control of Semiconductor Device Properties

MRS Bulletin ◽

10.1557/mrs2000.56 ◽

2000 ◽

Vol 25 (5) ◽

pp. 4-4

Keyword(s):

Organic Molecules ◽

Semiconductor Device ◽

Precise Control ◽

Device Properties

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Improvements in Electrical Properties of SiC Surface Using Mechano-Chemical Polishing

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.823 ◽

2008 ◽

Vol 600-603 ◽

pp. 823-826 ◽

Cited By ~ 12

Author(s):

Kazutoshi Hotta ◽

Kenji Hirose ◽

Yayoi Tanaka ◽

Kenji Kawata ◽

Osamu Eryu

Keyword(s):

Electrical Properties ◽

Epitaxial Growth ◽

Schottky Barrier ◽

Breakdown Voltage ◽

Semiconductor Device ◽

Atomic Level ◽

Schottky Barrier Diode ◽

Polished Surface ◽

Crystal Face ◽

The Past

To use SiC substrate as a semiconductor device and epitaxial growth, the surface of SiC substrate should be made smooth at an atomic level in the state of monocrystalline. But, the past slurry caused defects such as the pit and the scratch on the surface. This tendency was very strong in (000-1) C-face. We achieved ideal surface for SiC devices using newly developed slurry. In this surface, the roughness (Ra) of (0001) Si face and (000-1) C face evaluated by the AFM were 0.1nm or less, and confirmed that the surface were monocrystalline by CAICISS measurement. From these results, it is thought that the crystal face obtained by the slurry newly developed. In addition, the Schottky barrier diode was formed directly on the polished surface, that was obtained the breakdown voltage of 1.2kV or more. We thought that this results is possible to make the Schottky barrier diode without epitaxial growth.

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Atomic-level imaging of the surface structure of Ag2O

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100113160 ◽

1984 ◽

Vol 42 ◽

pp. 656-657

Author(s):

William Krakow

Keyword(s):

High Vacuum ◽

Atomic Level ◽

Ultra High Vacuum ◽

Research Groups ◽

Resolution Electron ◽

Surface Reconstructions ◽

Order Of Magnitude ◽

High Resolution Electron Microscope ◽

Saturated Structure ◽

Transmission And Reflection

In recent years electron microscopy has been used to image surfaces in both the transmission and reflection modes by many research groups. Some of this work has been performed under ultra high vacuum conditions (UHV) and apparent surface reconstructions observed. The level of resolution generally has been at least an order of magnitude worse than is necessary to visualize atoms directly and therefore the detailed atomic rearrangements of the surface are not known. The present author has achieved atomic level resolution under normal vacuum conditions of various Au surfaces. Unfortunately these samples were exposed to atmosphere and could not be cleaned in a standard high resolution electron microscope. The result obtained surfaces which were impurity stabilized and reveal the bulk lattice (1x1) type surface structures also encountered by other surface physics techniques under impure or overlayer contaminant conditions. It was therefore decided to study a system where exposure to air was unimportant by using a oxygen saturated structure, Ag2O, and seeking to find surface reconstructions, which will now be described.

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Defects in β-SiC thin films grown on α-SiC substrates

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010010490x ◽

1988 ◽

Vol 46 ◽

pp. 568-569

Author(s):

Karren L. More

Keyword(s):

Thin Films ◽

Semiconductor Device ◽

Lattice Mismatch ◽

Chemical Vapor ◽

Substrate Material ◽

Growth Interface ◽

Si Substrates ◽

Thermal Expansion Coefficients ◽

Device Applications ◽

Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

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Applications of SIMS to electronic materials and devices

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100133047 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1682-1683

Author(s):

S.F. Corcoran

Keyword(s):

Depth Distribution ◽

Secondary Ion Mass Spectrometry ◽

Semiconductor Device ◽

Electronic Materials ◽

Profile Analysis ◽

Semiconductor Industry ◽

Small Diameter ◽

Depth Resolution ◽

Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

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Structural and electronic properties of defects in semiconductors

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100136398 ◽

1995 ◽

Vol 53 ◽

pp. 4-5

Author(s):

J.L. Batstone

Keyword(s):

Semiconductor Device ◽

Chemical Vapor ◽

Misfit Strain ◽

Organic Chemical ◽

Extended Defects ◽

Transmission Electron ◽

Semiconductor Thin Films ◽

Wide Range ◽

Metal Organic ◽

Film Substrate

The development of growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy during the last fifteen years has resulted in the growth of high quality epitaxial semiconductor thin films for the semiconductor device industry. The III-V and II-VI semiconductors exhibit a wide range of fundamental band gap energies, enabling the fabrication of sophisticated optoelectronic devices such as lasers and electroluminescent displays. However, the radiative efficiency of such devices is strongly affected by the presence of optically and electrically active defects within the epitaxial layer; thus an understanding of factors influencing the defect densities is required.Extended defects such as dislocations, twins, stacking faults and grain boundaries can occur during epitaxial growth to relieve the misfit strain that builds up. Such defects can nucleate either at surfaces or thin film/substrate interfaces and the growth and nucleation events can be determined by in situ transmission electron microscopy (TEM).

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Metal Microstructures in Advanced CMOS Devices

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100164258 ◽

1996 ◽

Vol 54 ◽

pp. 358-359

Author(s):

L. M. Gignac ◽

K. P. Rodbell

Keyword(s):

Grain Boundaries ◽

Semiconductor Device ◽

Chemical Vapor ◽

Microstructural Characterization ◽

Metal Films ◽

Thin Metal ◽

Electrical Performance ◽

Thin Metal Films ◽

Chemical Vapor Deposited ◽

Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

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