Device Performance and Strain Effect of Sub-5 nm Monolayer InP Transistors

2022 ◽  
Author(s):  
Linqiang Xu ◽  
Ruge Quhe ◽  
Qiuhui Li ◽  
Shiqi Liu ◽  
Jie Yang ◽  
...  
Keyword(s):  
Indium Phosphide ◽  
Electron Mobility ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Strain Effect ◽  
Device Performance ◽  
Saturation Velocity ◽  
Effect Transistor

Indium phosphide (InP) has higher electron mobility, electron saturation velocity, and drain current than silicon (Si), and the ultra-thin (UT) InP field-effect transistor (FET) probably possesses a better device performance...

scholarly journals Growth and Device Performance of AlGaN/GaN Heterostructure with AlSiC Precoverage on Silicon Substrate

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
Jae-Hoon Lee ◽  
Jung-Hee Lee
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Film Growth ◽  
Drain Current ◽  
Device Performance ◽  
Wetting Layer ◽  
Si Substrate ◽  
Effect Transistor ◽  
Gan Heterostructure

A crack-free AlGaN/GaN heterostructure was grown on 4-inch Si (111) substrate with initial dot-like AlSiC precoverage layer. It is believed that introducing the AlSiC layer between AlN wetting layer and Si substrate is more effective in obtaining a compressively stressed film growth than conventional Al precoverage on Si surface. The metal semiconductor field effect transistor (MESFET), fabricated on the AlGaN/GaN heterostructure grown with the AlSiC layer, exhibited normally on characteristics, such as threshold voltage of −2.3 V, maximum drain current of 370 mA/mm, and transconductance of 124 mS/mm.

An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor

2020 ◽  
Vol 10 (2) ◽  
pp. 157-165
Author(s):  
Soumya S. Mohanty ◽  
Urmila Bhanja ◽  
Guru P. Mishra
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Model Simulation ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Short Channel ◽  
Effect Transistor ◽  
Rf Performance ◽  
Gate Underlap

Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the device simulation and it also includes Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed to analyze the various analog performance of device like drain current, surface potential, transconductance, threshold voltage, drain induced barrier lowering, off current, subthreshold slope, Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation factor and radio frequency performance of device, like trans-frequency product and cut-off frequency. Results: From the simulation, it can be observed that an improved analog and RF performance is obtained at the optimum underlap length. Conclusion: This work delivers an idea for extended researchers to investigate different aspects of group III–V underlap MOSFETs.

Double-Ion-Implanted GaN MESFETs with Extremely Low Source/Drain Resistance

2005 ◽  
Vol 892 ◽  
Author(s):  
Kazuki Nomoto ◽  
Nobuyuki Ito ◽  
Taku Tajima ◽  
Takeshi Kasai ◽  
Tomoyoshi Mishima ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Device Performance ◽  
Effect Transistor ◽  
State Resistance ◽  
Si Ion Implantation ◽  
Implanted Devices ◽  
Ion Implanted

AbstractIncorporation of Si ion implantation to GaN metal semiconductor field effect transistor (MESFET) processing has been demonstrated. The channel and source/drain regions formed using Si ion implantation into undoped GaN on sapphire substrate. In comparison with the conventional devices without ion implanted source/drain structures, the ion implanted devices showed excellent device performance. On-state resistance reduces from 210 Ω-mm to 105 Ω-mm. Saturation drain current and maximum transconductance increase from 36 mA/mm to 78 mA/mm and from 3.8 mS/mm to 10 mS/mm, respectively.

scholarly journals Diacenopentalene dicarboximides as new n-type organic semiconductors for field-effect transistors

2016 ◽  
Vol 4 (37) ◽  
pp. 8758-8764 ◽  
Author(s):  
Gaole Dai ◽  
Jingjing Chang ◽  
Linzhi Jing ◽  
Chunyan Chi
Keyword(s):  
Organic Semiconductors ◽  
Electron Mobility ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Processing Technique ◽  
Solution Processing ◽  
Effect Transistor

Two diacenopentalene dicarboximides were synthesized, and their devices made with solution-processing technique exhibited n-type field-effect transistor behavior with electron mobility of up to 0.06 cm2 V−1 s−1.

scholarly journals An Improved UU-MESFET with High Power Added Efficiency

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 573 ◽  
Author(s):  
Hujun Jia ◽  
Mei Hu ◽  
Shunwei Zhu
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
High Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
The Relationship

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

5A 1300V Trenched and Implanted 4H-SiC Vertical JFET

2012 ◽  
Vol 229-231 ◽  
pp. 824-827 ◽  
Author(s):  
Gang Chen ◽  
Xiao Feng Song ◽  
Song Bai ◽  
Li Li ◽  
Yun Li ◽  
...  
Keyword(s):  
Ohmic Contact ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Vertical Channel ◽  
Drain Current ◽  
Gate Bias ◽  
Blocking Voltage ◽  
Drain Bias ◽  
Effect Transistor ◽  
Lift Off

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.

Sign in / Sign up

Export Citation Format

Share Document