Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Muhammad Basit Azeem ◽  
Xinghua Wang
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Bone Block ◽  
Technological Advancement ◽  
Left Wing ◽  
Ultra Low Power ◽  
Content Type

Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Work Load ◽  
Input Voltage ◽  
Sar Adc ◽  
Power Circuit ◽  
Ultra Low Power ◽  
Content Type ◽  
Number Of Components

Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

scholarly journals A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Clock Generation ◽  
Analog Converter ◽  
Asynchronous Sar

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 203-214
Author(s):  
Pramod Kumar Patel ◽  
M.M. Malik ◽  
Tarun Kumar Gutpa
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Supply Voltage ◽  
Early Stage ◽  
Process Variation ◽  
High Density ◽  
Oxide Semiconductor ◽  
Mass Storage ◽  
Content Type ◽  
Sram Cell

Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells. Design/methodology/approach This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue. Findings The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart. Research limitations/implications Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit. Practical implications GNRFET devices are suitable for implementing low power and high density SRAM cell. Social implications The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices. Originality/value This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Maximum Delay ◽  
Average Power Consumption

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Challenges and Limitations of Low Power Techniques

2016 ◽  
pp. 48-70
Author(s):  
Vandana B. ◽  
Patro B. S.
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Semiconductor Device ◽  
Low Voltage ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Gate Length ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Contemporary World

In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.

A ± 0.2 V, 0.12 μW CCTA USING VTMOS AND AN APPLICATION FRACTIONAL-ORDER UNIVERSAL FILTER

2014 ◽  
Vol 23 (09) ◽  
pp. 1450126 ◽  
Author(s):  
TADA COMEDANG ◽  
PATTNA INTANI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Fractional Order ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Ultra Low Power ◽  
Variable Threshold ◽  
High Output Impedance

In this paper, a variable threshold voltage metal oxide semiconductor (VTMOS) field effect transistor is used to improve an ultra-low voltage, ultra-low power current conveyor transconductance amplifier (CCTA). To achieve the desired result, an analytical subthreshold VTMOS model is used. Designs that utilize the TSMC 0.18 μm technology are verified using PSPICE simulation. The power consumption is simply 0.12 μW at a ± 0.2 V supply voltage. The proposed CCTA is synthesized using fractional-order (FO) universal filters that can simultaneously realise low pass (LP), high pass (HP) and bandpass (BP) responses with independent control of quality factor and pole frequency by transconductances (gm). Moreover, the circuit has low input and high output impedance which would be an ideal choice for cascading in current-mode circuit. The FO filters are constructed using two FO capacitors of orders α and β (0 < α, β ≤ 1). The FO filters provide improved performance in terms of pole frequency compared with conventional-order filters. The filter has a low power consumption of 0.71 μW at a ± 0.2 V supply voltage. The validity of the proposed filter is verified through PSPICE simulations.

Performance analysis of multi-scaling voltage level shifter for low-power applications

2020 ◽  
Vol 17 (6) ◽  
pp. 803-809
Author(s):  
Vaithiyanathan D. ◽  
Megha Singh Kurmi ◽  
Alok Kumar Mishra ◽  
Britto Pari J.
Keyword(s):  
Low Power ◽  
Output Voltage ◽  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Voltage Level ◽  
Content Type ◽  
Level Shifter

Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

An Ultra-Low Power Subthreshold CMOS RSSI for Wake-Up Receiver

2016 ◽  
Vol 25 (08) ◽  
pp. 1650090 ◽  
Author(s):  
Yunzhen Wang ◽  
Shengxi Diao ◽  
Fujiang Lin ◽  
Haiquan Yuan
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Limiting Amplifier ◽  
Offset Voltage

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45[Formula: see text]dB input dynamic range and [Formula: see text][Formula: see text]dB indicating error are achieved at 125[Formula: see text]KHz frequency. The prototype occupies an active area of 0.39[Formula: see text][Formula: see text][Formula: see text]0.28[Formula: see text]mm using CSMC 0.153-[Formula: see text]m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8[Formula: see text]V supply voltage, the overall current consumption is only 6[Formula: see text][Formula: see text]A.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Sign in / Sign up

Export Citation Format

Share Document