scholarly journals Edgebond and Edgefill Induced Loading Effect on Large WLCSP Thermal Cycling Performance

2020 ◽  
Vol 33 (2) ◽  
pp. 22-27
Author(s):  
Andy Hsiao ◽  
Greg Baty ◽  
Edward Ibe ◽  
Karl Loh ◽  
Steve Perng ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Degradation Mechanism ◽  
Stress Component ◽  
High Stress ◽  
Cycling Performance ◽  
Propagation Path ◽  
Wafer Level ◽  
Electron Backscattered Diffraction ◽  
Mechanical Cycling ◽  
Failure Location

Various external load conditions affecting components on electronic devices and modules are constant factors, which need to be considered for the component long-term reliability. Recently, to enhance the high stress component thermo-mechanical cycling performance, various types and configuration using edgebond and edgefill technology are introduced and tested. These applications induce a multi-axis loading condition, which alter the degradation mechanism and failure location during thermal cycling, which need closer investigation. In this study, high stress 12x12mm2 wafer level chip scale packages (WLCSP) were selected and subject to thermal cycling with full-edgebond, dot-edgebond and edgefill adhesive, which improves the characteristic lifecycle numbers base on the configurations, but altered the failure location due to different stress conditions. The -40 to 125oC thermal cycling profile revealed localized degradation per configuration during thermal cycling, showed a shift of the crack propagation path, based on full-edgebond, dot-edgebond and edgefill adhesive sample conditions. Through these series of observation, the interconnect thermal cycling degradation mechanisms are able to be explained. The correlation between the stress condition and microstructure are  presented and discussed based on Electron backscattered diffraction (EBSD) analysis.

Impact of Conformal Coating Induced Stress on Wafer Level Chip Scale Package Thermal Cycling Performance

2020 ◽  
Vol 33 (2) ◽  
pp. 7-13
Author(s):  
Andy Hsiao ◽  
Mohamed Sheikh ◽  
Karl Loh ◽  
Edward Ibe ◽  
Tae-Kyu Lee
Keyword(s):  
Thermal Cycling ◽  
Salt Spray ◽  
Cycling Performance ◽  
Cycle Performance ◽  
Wafer Level ◽  
Cycle Number ◽  
Chemical Contaminants ◽  
Conformal Coating ◽  
Chip Scale Package ◽  
Tension And Compression

Conformal coating is commonly used for harsh environment to protect electronics from moisture and chemical contaminants. But the stresses imparted by the conformal coating can cause degradation to the package thermal cycle performance. Full coverage of the component with conformal coating material can prevent potential corrosion induced degradation but imply a local compression stress during thermal cycling, resulting a different thermal cycling performance compared to non-coated components. In this study, 8x8mm2 wafer level chip scale packages (WLCSP) were subjected to 5% NaCl aqueous spray test with and without full conformal coating, then thermal cycled from -40ºC to +125ºC. Weibull reliability statistics indicated that fully conformal coated components experience characteristic life cycle number reduction from 404 cycles to 307 cycles, a 24% lifetime reduction, comparing to no conformal coated, no salt spray test applied components. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and electro-backscattered diffraction, which revealed that the conformal coating induced a z-axis tension and compression strain during thermal cycling, resulting in an accelerated degradation at the solder interconnect. Linear Laser profilometer measurements showed that fully conformal coated samples experienced a higher z-axis height displacement change relative to non-conformal coated samples when exposed to 125 °C with 10 minutes dwell. To prevent this z-axis strain a reworkable edgebond adhesive was applied with full conformal coating configuration, which demonstrate an increase of characteristic lifecycle number to 2783 cycles, suggesting that the mitigation of the z-axis strain can vastly enhance the thermal cycling performance.

Effect of Mechanical and Thermal Cycling on Shape Memory Properties of High Temperature Cu-Al-Ni Single Crystals

Aerospace ◽  
2004 ◽  
Author(s):  
Ganesh K. Kannarpady ◽  
A. Bhattacharyya
Keyword(s):  
Ambient Temperature ◽  
Thermal Cycling ◽  
Single Crystal ◽  
Shape Memory ◽  
High Stress ◽  
Transformation Temperatures ◽  
Ambient Temperatures ◽  
Temperature Range ◽  
Mechanical Cycling ◽  
Downward Shift

With a view towards applications as actuators, the effect of mechanical cycling followed by thermal cycling on 1.5 mm diameter Cu-13.3%Al-4%Ni (by weight) single crystal wires with high stress-free transformation temperatures: Mf = 96°C, Ms = 105.5°C, As = 111.6°C and Af = 115.8°C (determined by the method of tangents) have been studied at different ambient temperatures in the range 25–125°C. The tests are carried out in an Instron machine with an environmental chamber. Stress cycling at a given ambient temperature was carried out for an overall strain of 9% until the stress-strain curves became fairly repeatable. A total of 35 stress cycles were needed to span the ambient temperature range, 25–125°C. The material showed an excellent retention of the shape memory effect in the range of 25–100°C (this is below the Af = 115.8°C of the as-received sample), excellent pseudoelasticity at 125°C, and no irreversible plastic deformation. A net downward shift of transformation temperatures by about 5°C did occur over the first 11 cycles. This was followed by a reversal of the downward shift and the transformation temperatures stabilized by the 35th cycle close to those of the as-received sample. The stabilized temperatures were: Mf = 95°C, Ms = 106.5°C, As = 110°C and Af = 118.5°C (method of tangents). However, the transformation occurred over a wider temperature range as compared to that of the as-received sample, especially during the austenite to martensite transformation on cooling. These features point to the possibility of the Cu-13.3%Al-4%Ni single crystal as a highly competitive candidate for actuator applications.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

A Highly Accelerated Thermal Cycling (HATC) Test for Solder Reliability Assessment in BGA Packages

2007 ◽  
Author(s):  
X. Long ◽  
I. Dutta ◽  
R. Guduru ◽  
R. Prasanna ◽  
M. Pacheco
Keyword(s):  
Thermal Cycling ◽  
Solder Joints ◽  
Low Cycle Fatigue ◽  
Inelastic Strain ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Mechanical Cycling ◽  
Experimental Apparatus ◽  
Dependent Strain ◽  
Accelerated Thermal Cycling

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

Cycling performance of LiFePO4/graphite batteries and their degradation mechanism analysis via electrochemical and microscopic techniques

Ionics ◽  
2021 ◽  
Author(s):  
Hossein Sharifi ◽  
Behrooz Mosallanejad ◽  
Mohammadkhalil Mohammadzad ◽  
Seyed Morteza Hosseini-Hosseinabad ◽  
Seeram Ramakrishna
Keyword(s):  
Degradation Mechanism ◽  
Cycling Performance ◽  
Mechanism Analysis ◽  
Microscopic Techniques

Active and Passive Devices Embedded in Laminate-Based Multilayer Board

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao
Keyword(s):  
High Temperature ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Wafer Level ◽  
Active Device ◽  
Electrical Connection ◽  
Passive Devices ◽  
High Temperature Storage ◽  
Circuit Resistance ◽  
Temperature Storage

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.

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