An embedded DRAM-FPGA chip with instantaneous logic reconfiguration

2002 ◽  
Author(s):  
M. Motomura ◽  
Y. Aimoto ◽  
A. Shibayama ◽  
Y. Yabe ◽  
M. Yamashina
Keyword(s):  
Fpga Chip

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

Research and Design of Digital Clock Based on FPGA

2011 ◽  
Vol 187 ◽  
pp. 741-745 ◽  
Author(s):  
Juan Hua Zhu ◽  
Ang Wu ◽  
Juan Fang Zhu
Keyword(s):  
Design Method ◽  
Display Time ◽  
Development Environment ◽  
Display Module ◽  
Digital Clock ◽  
Clock System ◽  
Quartus Ii ◽  
Hardware Description ◽  
Fpga Chip ◽  
Led Lights

A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.

Application of Arithmetic Operations Method in Single Pair-Pole Magnetic Encoder

2011 ◽  
Vol 128-129 ◽  
pp. 85-91
Author(s):  
Yi Fan Zeng ◽  
Rui Li
Keyword(s):  
High Speed ◽  
Angle Measurement ◽  
Single Pair ◽  
Nonlinear Correction ◽  
Arithmetic Operations ◽  
Rotational Angle ◽  
Voltage Signal ◽  
Fpga Chip ◽  
Novel Method ◽  
Hall Sensors

This paper proposes a novel method called arithmetic operations to analyze and process the generated voltage-signal from the single pair-pole magnetic encoder. Dual orthogonal voltage-signals are generated by two vertical hall sensors which are placed in the bottom of a columned magnet. When signals pass A/D converter, the quadrant determination, arithmetic operations and nonlinear correction in FPGA chip are performed before the values of rotational angle are displayed on the LED. This paper also designs and implements the single pair-pole magnetic encoder which has advantages such as high-speed, high-resolution and high-accuracy in the area of angle measurement.

Protocol Design for Free Space Optical (FSO) Communication

2015 ◽  
Vol 738-739 ◽  
pp. 1178-1184
Author(s):  
Ru Hai Guo ◽  
Chang Shun Liu ◽  
Heng Kun Wang ◽  
Jin Wu ◽  
Jun Feng Chong
Keyword(s):  
Free Space ◽  
Data Stream ◽  
Great Influence ◽  
Exception Handling ◽  
Free Space Optical ◽  
System Integrity ◽  
Serial Data ◽  
Fpga Chip ◽  
Signal Channel ◽  
Wired Communication

A new transceiving protocol is designed for an FSO communication system, and it’s discussed from the transmitting protocol and the receiving protocol. Different from wired communication, a FSO system modulates the data on a narrow beam of laser transmitting through the free space or the atmosphere, and the protocol is optimized for terrestrial FSO links. Due to the complex composition and activity of the atmosphere, this signal channel brings in great influence on the transmitting laser in it. The function of the receiving protocol includes filtering and synchronizing the input serial data stream, paralleling the serial data stream, decoding the input data, error checking, and exception handling and interfacing the outer receiver with a parallel port. The transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. We also test the hardware platform and communication protocol and give the waveform. The experiment and Simulation prove that the protocol presented can work well at a certain bit rate scale.

The Predigest Project of Vehicle-Bone Multimedia Transmission and Control Network Based on FPGA

2012 ◽  
Vol 203 ◽  
pp. 62-66
Author(s):  
Hong Li ◽  
Qiao Zhen Hou
Keyword(s):  
Network Control ◽  
Control Network ◽  
Network System ◽  
Multimedia Transmission ◽  
Transmission Control ◽  
Hardware Platform ◽  
Arm Processor ◽  
Interface Module ◽  
Fpga Chip ◽  
And Control

The design uses 32 ARM processor S3C44B0X and Spartan™ -3E500 FPGA chip produced by Xinlinx company for setting up the hardware platform, and integrates the camera, GPS module, MiniGUI interface module. And realized bus vehicle mounted multimedia transmission control network control based on MOST. All of these are in the purpose of achieving a Predigest Project of vehicle-bone multimedia transmission and control network based on FPGA. The experiment indicated that, the transmission and control network system constructed by S3C44B0X and Spartan - 3E500 FPGA is low cast, simple and reliable.

Automatic Frequency-Tracking Control for Ultrasound Welding System

2011 ◽  
Vol 204-210 ◽  
pp. 2041-2044
Author(s):  
Kao Feng Yarn ◽  
King Kung Wu ◽  
Kai Hsing Ma ◽  
Wen Chung Chang
Keyword(s):  
High Power ◽  
Tracking Control ◽  
Control Method ◽  
Ultrasonic Welding ◽  
Automatic Frequency ◽  
Frequency Tracking ◽  
Power Ultrasonic ◽  
Fpga Chip ◽  
Working Frequency ◽  
Welding System

A new frequency-tracking control method to catch the optimal working frequency for the high power ultrasonic welding system is proposed. In a high power ultrasonic resonant system, the induced high temperature will change the working frequency. Therefore, the proposed control method to track the optimal working frequency becomes very attractive and important. This control method is practically implemented by a FPGA chip which basically includes two logic circuits. One logic circuit is to find the optimal working frequency automatically and the other one is to adjust the working frequency by detecting the working current simultaneously. Experimental results exhibit the new method can effectively control and track frequency for high power ultrasonic welding system.

scholarly journals High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

2017 ◽  
Vol 7 (1) ◽  
pp. 52 ◽  
Author(s):  
Hai Wang ◽  
Min Zhang ◽  
Yan Liu
Keyword(s):  
High Resolution ◽  
Fpga Chip

scholarly journals An FPGA Chip Identification Generator Using Configurable Ring Oscillators

2012 ◽  
Vol 20 (12) ◽  
pp. 2198-2207 ◽  
Author(s):  
Haile Yu ◽  
Philip H. W. Leong ◽  
Qiang Xu
Keyword(s):  
Ring Oscillators ◽  
Fpga Chip

scholarly journals A Flexible FPGA-Based Channel Emulator for Non-Stationary MIMO Fading Channels

2020 ◽  
Vol 10 (12) ◽  
pp. 4161
Author(s):  
Qiuming Zhu ◽  
Wei Huang ◽  
Kai Mao ◽  
Weizhi Zhong ◽  
Boyu Hua ◽  
...  
Keyword(s):  
Fading Channels ◽  
Channel Model ◽  
Multiple Input Multiple Output ◽  
Mimo Channel ◽  
Channel Fading ◽  
Power Delay Profile ◽  
Channel Emulator ◽  
Field Programmable ◽  
Fpga Chip ◽  
Doppler Power

In this paper, a discrete non-stationary multiple-input multiple-output (MIMO) channel model suitable for the fixed-point realization on the field-programmable gate array (FPGA) hardware platform is proposed. On this basis, we develop a flexible hardware architecture with configurable channel parameters and implement it on a non-stationary MIMO channel emulator in a single FPGA chip. In addition, an improved non-stationary channel emulation method is employed to guarantee accurate channel fading and phase, and the schemes of other key modules are also illustrated and implemented in a single FPGA chip. Hardware tests demonstrate that the output statistical properties of proposed channel emulator, i.e., the probability density function (PDF), cross-correlation function (CCF), Doppler power spectrum density (DPSD), and the power delay profile (PDP) agree well with the corresponding theoretical ones.

The Design of Step Motor Subdivision Drive Controller Based on FPGA

2014 ◽  
Vol 577 ◽  
pp. 378-381 ◽  
Author(s):  
Hong Yan Dong ◽  
Hong Min Guo
Keyword(s):  
Step Motor ◽  
Stepper Motor ◽  
Stepping Motor ◽  
Software Platform ◽  
Simulation Test ◽  
Fpga Chip ◽  
Optimization And Simulation

This paper, based on the EDA software platform and VHDL description method, introduces how to use the FPGA chip to control the multiphase stepper motor. This design, through automatic logic compilation optimization and simulation test and compile, finally completed the function of the stepping motor subdivision drive controller. By testing, it can achieve controlling positive &negative and subdivision for stepper angle.

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