A SEU/MBU tolerant SRAM bit cell based on multi-input gate

2017 ◽  
Author(s):  
Zou Sanyong
Keyword(s):  
Input Gate

scholarly journals A new image encryption algorithm based on the OF-LSTMS and chaotic sequences

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yi He ◽  
Ying-Qian Zhang ◽  
Xin He ◽  
Xing-Yuan Wang
Keyword(s):  
Image Encryption ◽  
Fractional Order ◽  
Chaotic System ◽  
Short Term Memory ◽  
Encryption Algorithm ◽  
Chaotic Sequences ◽  
Long Short Term Memory ◽  
Input Gate ◽  
And Diffusion ◽  
Image Encryption Algorithm

AbstractIn this paper, a novel image encryption algorithm based on the Once Forward Long Short Term Memory Structure (OF-LSTMS) and the Two-Dimensional Coupled Map Lattice (2DCML) fractional-order chaotic system is proposed. The original image is divided into several image blocks, each of which is input into the OF-LSTMS as a pixel sub-sequence. According to the chaotic sequences generated by the 2DCML fractional-order chaotic system, the parameters of the input gate, output gate and memory unit of the OF-LSTMS are initialized, and the pixel positions are changed at the same time of changing the pixel values, achieving the synchronization of permutation and diffusion operations, which greatly improves the efficiency of image encryption and reduces the time consumption. In addition the 2DCML fractional-order chaotic system has better chaotic ergodicity and the values of chaotic sequences are larger than the traditional chaotic system. Therefore, it is very suitable to image encryption. Many simulation results show that the proposed scheme has higher security and efficiency comparing with previous schemes.

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

scholarly journals A Reconsideration of the Mass Balance of a Portion of the Ross Ice Shelf, Antarctica

1984 ◽  
Vol 30 (106) ◽  
pp. 381-384 ◽  
Author(s):  
Kenneth C. Jezek ◽  
Charles R. Bentley
Keyword(s):  
Mass Balance ◽  
Small Region ◽  
Volume Element ◽  
Ice Shelf ◽  
Ross Ice Shelf ◽  
The North ◽  
Ice Velocity ◽  
Flow Band ◽  
Input Gate ◽  
North Western

AbstractThe identification of a small region of grounded ice in the north-western sector of the Ross Ice Shelf has forced a re-evaluation of the mass-balance calculations carried out by Thomas and Bentley (1978). Those authors concluded that the Ross Ice Shelf up-stream of Crary Ice Rise was thickening, but they did not take into account the effects on the velocity field of grounded ice (of which they were unaware), which is located near the input gate to their volume element. Reasonable estimates of the degree to which the ice velocity just up-stream of the grounded ice is diminished indicate that it is no longer possible to conclude that the ice shelf is thickening using Thomas and Bentley’s original flow band. Therefore, a new flow band was chosen which was grid east of Thomas and Bentley’s band and unaffected by any nearby grounded areas. The mass balance in this flow band was found to be zero within experimental error; a difference exceeding about 0.2 m a−1 in magnitude between the thickening and bottom freeze-on rates is unlikely.

A novel long short-term memory network for lithium-ion battery health diagnosis using charging curve

2021 ◽  
pp. 014233122110409
Author(s):  
Mingqiang Lin ◽  
Denggao Wu ◽  
Gengfeng Zheng ◽  
Ji Wu
Keyword(s):  
Lithium Ion Batteries ◽  
Short Term Memory ◽  
Lithium Ion ◽  
Short Term ◽  
Data Set ◽  
Term Memory ◽  
Battery Degradation ◽  
Memory Network ◽  
Long Short Term Memory ◽  
Input Gate

Lithium-ion batteries are widely used as the power source in electric vehicles. The state of health (SOH) diagnosis is very important for the safety and storage capacity of lithium-ion batteries. In order to accurately and robustly estimate lithium-ion battery SOH, a novel long short-term memory network (LSTM) based on the charging curve is proposed for SOH estimation in this work. Firstly, aging features that reflect the battery degradation phenomenon are extracted from the charging curves. Then, considering capture the long-term tendency of battery degradation, some improvements are made in the proposed LSTM model. The connection between the input gate and the output gate is added to better control output information of the memory cell. Meanwhile, the forget gate and input gate are coupled into a single update gate for selectively forgetting before the accumulation of information. To achieve more reliability and robustness of the SOH estimation method, the improved LSTM network is adaptively trained online by using a particle filter. Furthermore, to verify the effectiveness of the proposed method, we compare the proposed method with two data-driven methods on the public battery data set and the commercial battery data set. Experimental results demonstrate the proposed method can obtain the highest SOH accuracy.

IMPACT OF GATE POLYSILICON INTERFACE ON CARRIER TRAPPING LOW FREQUENCY NOISE IN ADVANCED MOSFET'S

2006 ◽  
Vol 06 (04) ◽  
pp. L427-L432 ◽  
Author(s):  
G. GHIBAUDO ◽  
J. JOMAAH ◽  
F. BALESTRA
Keyword(s):  
Noise Analysis ◽  
Low Frequency ◽  
Drain Current ◽  
Oxide Thickness ◽  
Frequency Noise ◽  
Oxide Interface ◽  
Carrier Trapping ◽  
Noise Characteristics ◽  
Input Gate ◽  
The Impact

In this work, we calculate, for the first time, the impact of carrier trapping at the gate polysilicon/oxide interface on the LF noise characteristics of polygate MOSFET's. After extending the channel LF noise analysis, based on carrier number and correlated mobility fluctuations approaches, to include charge variations at the polySi/oxide interface, we derive analytical expressions accounting for the impact of fluctuations of poly/oxide interfacial charge on the channel drain current and input gate voltage noise as a function of gate bias, polysilicon doping concentration and gate oxide thickness.

scholarly journals Efficient Decomposition of Unitary Matrices in Quantum Circuit Compilers

2022 ◽  
Vol 12 (2) ◽  
pp. 759
Author(s):  
Anna M. Krol ◽  
Aritra Sarkar ◽  
Imran Ashraf ◽  
Zaid Al-Ars ◽  
Koen Bertels
Keyword(s):  
Quantum Algorithms ◽  
Optimization Method ◽  
Quantum Circuit ◽  
Quantum Gates ◽  
Underlying Structure ◽  
Quantum Computers ◽  
Unitary Matrices ◽  
Quantum Operations ◽  
Test Part ◽  
Input Gate

Unitary decomposition is a widely used method to map quantum algorithms to an arbitrary set of quantum gates. Efficient implementation of this decomposition allows for the translation of bigger unitary gates into elementary quantum operations, which is key to executing these algorithms on existing quantum computers. The decomposition can be used as an aggressive optimization method for the whole circuit, as well as to test part of an algorithm on a quantum accelerator. For the selection and implementation of the decomposition algorithm, perfect qubits are assumed. We base our decomposition technique on Quantum Shannon Decomposition, which generates O(344n) controlled-not gates for an n-qubit input gate. In addition, we implement optimizations to take advantage of the potential underlying structure in the input or intermediate matrices, as well as to minimize the execution time of the decomposition. Comparing our implementation to Qubiter and the UniversalQCompiler (UQC), we show that our implementation generates circuits that are much shorter than those of Qubiter and not much longer than the UQC. At the same time, it is also up to 10 times as fast as Qubiter and about 500 times as fast as the UQC.

scholarly journals PROTOYPE GERBANG LOGIKA ( AND, OR, NOT, NAND, NOR ) PADA LABORATORIUM ELEKTRONIKA STMIK ROYAL KISARAN

2017 ◽  
Vol 1 (1) ◽  
pp. 37
Author(s):  
Helmi Fauzi Siregar ◽  
Ikhsan Parinduri
Keyword(s):  
Learning Process ◽  
Teaching And Learning ◽  
Logic Gate ◽  
Logic Gates ◽  
Digital Circuit ◽  
Nand Gate ◽  
Abstract Logic ◽  
Working Principle ◽  
Input Gate ◽  
Or Gate

Abstract - Logic gate prototype aims to meet the needs and smoothness of the teaching and learning process in one of the digital circuit lecture materials. Proof of the logic of OR, AND, NOT, NOR, and NAND gates. The working principle of logic gate prototype is working based on input logic including 0 and 1. For AND logic gates are input multiplication gates consisting of (0,0, 0,1, 1,0, 1,1) and output consists of 1 for high (1) and 3 for low (0). For OR gate is the input sum gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For the NAND gate is the logic inverting gate of the AND input gate consisting of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For NOR input logic gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 1 for high (1) and 3 for low (0). For the NOT gate is the inverse gate with input (1, 0) and the output consists of (0,1). Keywords - Logic Gate, Prototype, OR, AND, NOT, NOR, NAND

Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors

1996 ◽  
Vol 8 (6) ◽  
pp. 508-515 ◽  
Author(s):  
Tadashi Shibata ◽  
◽  
Tadahiro Ohmi
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Intelligent Systems ◽  
Circuit Complexity ◽  
Primary Objective ◽  
Electronic Circuits ◽  
Circuit Element ◽  
Hardware Configuration ◽  
Input Gate ◽  
Intelligent Data Processing

The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.

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