A Configurable, Multi-Mode Comma Detection and Word Alignment Controller for High Speed Serial Interface in 130 nm CMOS Technology

2018 ◽  
Author(s):  
Imran Ali ◽  
Muhammad Asif ◽  
Muhammad Riaz Ur Rehman ◽  
Muhammad Basim ◽  
Sung Jin Kim ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Word Alignment ◽  
Serial Interface ◽  
Multi Mode

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

2013 ◽  
Vol 364 ◽  
pp. 439-443
Author(s):  
Xue Fei Jiang ◽  
Xiang Ning Fan
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Frequency Range ◽  
Dual Mode ◽  
Hardware Cost ◽  
Operating Frequency Range ◽  
Pll Frequency Synthesizer ◽  
Multi Mode

A architecture of multi-mode PLL frequency synthesizer one can meet a variety of communication standards is presented in this paper, which can provide each mode with the required frequency, while reducing the system's hardware cost. Optimized broadband high-speed dual-mode prescaler (DMP)'s internal structure, the principle of circuit design and its layout is introduced. The DMP is produced by 0.18μm CMOS technology. The post simulation results show that with the 1.8V power, the DMP's operating frequency range is 0.4 ~ 9.6GHz, the power consumption is 7.6mA.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Prediction of chatter stability in high-speed finishing end milling considering multi-mode dynamics

2009 ◽  
Vol 209 (5) ◽  
pp. 2585-2591 ◽  
Author(s):  
W.X. Tang ◽  
Q.H. Song ◽  
S.Q. Yu ◽  
S.S. Sun ◽  
B.B. Li ◽  
...  
Keyword(s):  
High Speed ◽  
End Milling ◽  
Chatter Stability ◽  
Multi Mode

A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

2022 ◽  
Vol 17 (01) ◽  
pp. C01040
Author(s):  
C. Zhao ◽  
D. Guo ◽  
Q. Chen ◽  
N. Fang ◽  
Y. Gan ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Test Results ◽  
Eye Diagram ◽  
Optical Links ◽  
Optical Module ◽  
Active Feedback ◽  
High Bandwidth ◽  
Output Driver ◽  
Very High

Abstract This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

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