Study and modeling of defects in integrated circuits for their reliability analysis

Author(s):  
G. Ait Abdelmalek ◽  
R. Ziani ◽  
M. Laghrouche
2005 ◽  
Vol 98 (3) ◽  
pp. 034503 ◽  
Author(s):  
Gaddi S. Haase ◽  
Ennis T. Ogawa ◽  
Joe W. McPherson

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550006 ◽  
Author(s):  
Leila Ladani

Through silicon vias (TSVs) play a critical role in today’s microelectronic technology as they enable fabrication of three-dimensional integrated circuits. Traditionally, copper has been used to fill TSVs. However, copper is prone to electro-migration and as the size of TSVs become smaller, copper resistance increases significantly, thereby reducing its potential for TSV material at nanoscales. A proposed hybrid structure is presented here in which Carbon Nanotube (CNT) bundles are grown vertically inside TSVs and encased with copper. The CNT bundles assists with increasing the strength of the hybrid structure and is likely to enhance the reliability of the package. Thermo-mechanical stress analysis and reliability evaluations is conducted to determine the effect of CNT bundles on stress distribution in the package and their impact on reliability of other critical components such as solder bumps that are used to join the silicon layers. The finite element analysis shows that addition of CNT material to the structure, even in small volume ratios tend to redistribute the stress and refocus it to inside the CNT material rather than interfaces. Interface stresses in low strength material typically cause delamination and failure in the package. Redistribution of stress is likely to enhance the reliability of the TSVs. Additional reliability analysis of the solder joints, shows that CNT additions enhances the number of cycles to failure four times. It is hypothesized that addition of CNTs decreases the local CTE mismatch between the silicon layers and assists in reducing the stress in solder bumps. This hypothesis is proven using finite element simulations.


2014 ◽  
Vol 2014 ◽  
pp. 1-9
Author(s):  
N. S. S. Singh

As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. As a result, several computational methodologies have been proposed to evaluate reliability of those circuit systems. However, the process of computing reliability has become very time consuming and troublesome as the computational complexity grows exponentially with the dimension of circuit systems. Therefore, being able to speed up the task of reliability analysis is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into developing a MATLAB-based automated reliability tool by incorporating the generalized form of the existing computational approaches that can be found in the current literature. Secondly, a comparative study involving those existing computational approaches is carried out on a set of standard benchmark test circuits. Finally, the paper continues to find the exact error bound for individual faulty gates as it plays a significant role in the reliability of circuit systems.


Author(s):  
Simon Thomas

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.


Author(s):  
L.J. Chen ◽  
Y.F. Hsieh

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.


Author(s):  
E.D. Wolf

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.


Author(s):  
John R. Devaney

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.


Author(s):  
N. Rozhanski ◽  
V. Lifshitz

Thin films of amorphous Ni-Nb alloys are of interest since they can be used as diffusion barriers for integrated circuits on Si. A native SiO2 layer is an effective barrier for Ni diffusion but it deformation during the crystallization of the alloy film lead to the appearence of diffusion fluxes through it and the following formation of silicides. This study concerns the direct evidence of the action of stresses in the process of the crystallization of Ni-Nb films on Si and the structure of forming NiSi2 islands.


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