Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 μm CMOS technology

2002 ◽  
Author(s):  
R. Difrenza ◽  
P. Llinares ◽  
E. Granger ◽  
H. Brut ◽  
G. Ghibaudo
Keyword(s):  
Oxide Thickness ◽  
Cmos Technology

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Impact of temperature and breakdown statistics on reliability predictions for ultrathin oxides

1999 ◽  
Vol 592 ◽  
Author(s):  
G. Groeseneken ◽  
R. Degraeve ◽  
B. Kaczer ◽  
H.E. Maes
Keyword(s):  
Oxide Thickness ◽  
Cmos Technology ◽  
Percolation Model ◽  
Strong Increase ◽  
Combined Effects ◽  
Technology Scaling ◽  
Test Methodology ◽  
Oxide Reliability ◽  
Ultrathin Oxides ◽  
The Impact

ABSTRACTThis paper discusses the evolution in the degradation and breakdown behaviour of ultra-thin oxides when scaling the oxide thickness into the sub-4 nm range for future CMOS technology generations. It will be shown that changes in the breakdown statistics, which can be explained by a percolation model for breakdown, lead to an increased area dependence of the time-tobreakdown. This has to be taken into account when predicting the oxide reliability. Also the impact of the test methodology, the relevance of a so-called polarity gap in the charge-tobreakdown and its consequences for reliability testing, are highlighted. Moreover, a strong increase in the temperature dependence of breakdown, especially for sub-3 nm oxides, is demonstrated and the impact of temperature on trap generation and critical trap density at breakdown is discussed. Finally it is shown that the combined effects of all these phenomena might lead to oxide reliability becoming a potential showstopper for further technology scaling.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

RTS Noise of CMOS Technology

2011 ◽  
Vol 465 ◽  
pp. 334-337
Author(s):  
Miloš Chvátal ◽  
Jan Pavelka ◽  
Vlasta Sedláková ◽  
Tomas Trčka ◽  
Pavel Škarvada
Keyword(s):  
Electric Field ◽  
Time Constant ◽  
Drain Current ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Current Component ◽  
Capture Time ◽  
Gate Oxide Thickness ◽  
Drain Electrode ◽  
Rts Noise

Experiments were carried out for n-channel devices, processed in a 300 nm CMOS technology. The investigated devices have a gate oxide thickness of 6 nm and the effective interface area is AG = 1.5 m2. The RTS measurements were performed for constant gate voltage, where the drain current was changed by varying the drain voltage. The capture time constant increases with increasing drain current. The model explaining the experimentally observed capture time constant dependence on the lateral electric field and the trap position is given. From the dependence of the capture time constant c on the drain current we can calculate x-coordinate of the trap position. Electron concentration in the channel decreases linearly from the source to the drain contact. Diffusion current component is independent on the x-coordinate and it is equal to the drift current component for the low electric field. Lateral component of the electric field intensity is inhomogeneous in the channel and it has a minimum value near the source contact and increases with the distance from the source to the drain. It reaches maximum value near the drain electrode.

Epitaxial Lanthanide Oxide based Gate Dielectrics

2009 ◽  
Vol 1155 ◽  
Author(s):  
H. Jörg Osten ◽  
Apurba Laha ◽  
Andreas Fissel
Keyword(s):  
Dielectric Properties ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Field Effect Transistors ◽  
Electrical Breakdown ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Leakage Currents ◽  
Good Reliability ◽  
The Impact

AbstractMany materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm CMOS technology. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. On Si(100), crystalline Gd2O3 grows usually as (110)-oriented domains, with two orthogonal in-plane orientations. Layers grown under best vacuum conditions often exhibit poor dielectric properties due to the formation of crystalline interfacial silicide inclusions. Additional oxygen supply during growth improves the dielectric properties significantly. Layers grown by an optimized MBE process display a sufficiently high-K value to achieve equivalent oxide thickness values < 1 nm, combined with ultra-low leakage current densities, good reliability, and high electrical breakdown voltage. A variety of MOS capacitors and field effect transistors has been fabricated based on these layers. Efficient manipulation of Si(100) 4° miscut substrate surfaces can lead to single domain epitaxial Gd2O3 layer. Such epi-Gd2O3 layers exhibited significant lower leakage currents compared to the commonly obtained epitaxial layers with two orthogonal domains. For capacitance equivalent thicknesses below 1 nm, this differences disappear, indicating that for ultrathin layers direct tunneling becomes dominating. We investigated the effect of post-growth annealings on layer properties. We showed that a standard forming gas anneal can eliminate flatband instabilities and hysteresis as well as reduce leakage currents by saturating dangling bond caused by the bonding mismatch. In addition, we investigated the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si with different orientations. The degradation of layers can be significantly reduced by sealing the layer with amorphous silicon prior to annealing.

An Advanced High-k Transistor Utilizing Metal-Organic Precursors in an ALD Deposition of Hafnium Oxide and Hafnium Silicate with Ozone as Oxidizer

2004 ◽  
Vol 811 ◽  
Author(s):  
J. Gutt ◽  
G.A. Brown ◽  
Yoshi Senzaki ◽  
Seung Park
Keyword(s):  
Hafnium Oxide ◽  
High Performance ◽  
Gate Dielectric ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Hafnium Silicate ◽  
High K ◽  
Metal Organic

AbstractThe International Technology Roadmap for Semiconductors (ITRS) has projected that continued scaling of planar CMOS technology to the 65nm node and beyond will require development of high-k films for transistor gate dielectric applications to allow further scaling of overall device sizes according to Moore's Law [1]. Researchers have recently been studying hafnium-based high-k dielectrics as an alternative to SiO2 [2]. The method of deposition of these films has been found to impact the applicability of the films for both low standby power and high performance applications [3]. Atomic Layer Deposition (ALD) has been among the more widely studied deposition techniques for these films, but previous work has emphasized ALD utilizing inorganic precursors [4]. In this paper, we shall describe a process in which hafnium oxide and hafnium silicate films were deposited from alternating pulses of volatile metal-organic Hf/Si liquid precursors and ozone on 200mm diameter Si substrates using a single wafer ALD system. Electrical characterization of the films is presented, including equivalent oxide thickness (EOT), gate leakage, and electron mobility data, showing an achievement of EOT's ranging from 1.19 to 1.69 nm with high field mobilities from 74% to more than 90% of that of SiO2 (2.1 nm film), and Jg in the range of 80mA to 3 A/cm2.

Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology

2002 ◽  
Vol 716 ◽  
Author(s):  
Abhisek Dixit ◽  
Rajiv O. Dusane ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Voltage ◽  
High Performance ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Channel Length ◽  
Short Channel ◽  
Channel Effects ◽  
Deep Source ◽  
Proper Scaling ◽  
Effective Channel

AbstractDegrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.

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