Wafer bonding using parylene and wafer-level transfer of free-standing parylene membranes

Author(s):  
H.S. Kim ◽  
K. Najafi
2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.


2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  

2018 ◽  
Vol 86 (5) ◽  
pp. 145-158 ◽  
Author(s):  
Thomas Plach ◽  
Bernhard Rebhan ◽  
Viorel Dragoi ◽  
Thomas Wagenleitner ◽  
Markus Wimplinger ◽  
...  

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.


2005 ◽  
Vol 127 (1) ◽  
pp. 7-11 ◽  
Author(s):  
A. Polyakov ◽  
M. Bartek ◽  
J. N. Burghartz

This paper reports on an area-selective adhesive wafer bonding, using photosensitive BCB from Dow Co. The strength of the fabricated bonds is characterized using the wedge-opening and tensile methods. The measured fracture toughness is 53.5±3.9J/m2 with tensile strength up to 71 MPa. The potential application of BCB bonding is demonstrated on a concept of wafer-level chip-scale package for RF applications and microfilter array for microfluidic applications.


2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.


Author(s):  
Francisco Cadacio ◽  
Teng Wang ◽  
Abdellah Salahouelhadj ◽  
Giovanni Capuz ◽  
Goedele Potoms ◽  
...  

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