scholarly journals The IC's Surprising Birth

2000 ◽  
Vol 122 (06) ◽  
pp. 68-73
Author(s):  
George Rostky
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Design Teams ◽  
New Development ◽  
Market Leader ◽  
Silicon Transistor

This article reviews the origin and costs of integrated circuits in the semiconductor industry. Sometimes, a significant integrated circuit achievement might not receive history’s recognition because it simply did not work well. The market might politely applaud a new development, but if another came along that was considerably cheaper, it would be seized hungrily. It would become the market leader and later in history's eyes, might appear to have been first. Jean Hoerni from Fairchild Semiconductor, in Mountain View, CA, developed a new transistor with all parts on one plane. He made connections through an insulating and protecting layer of oxide. Fairchild formed two design teams, one under co-founder Cordon Moore, to develop NPN, and one under co-founder Hoerni, who was working for Moore, to develop PNPs. Both projects were successful—Moore’s NPN, the 2N967, the first high-performance silicon transistor, and Hoerni’s PNP, the 2Nl132. But the NPN was easier to make at first, so Moore chose that one for IBM. Today, ICs house millions of transistors at costs of a fraction of a mil per transistor.

Metallization for Integrated Circuit Manufacturing

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 33-37 ◽  
Author(s):  
R.V. Joshi ◽  
R.S. Blewer ◽  
S. Murarka
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Random Access ◽  
Circuit Performance ◽  
Integrated Circuit Manufacturing ◽  
The 1960S ◽  
Al Metallization

This issue of the MRS Bulletin focuses on current interconnect metallurgies practiced in the manufacturing of integrated circuits (ICs). The issue should serve as a reference for researchers, scientists, engineers, and those who are not familiar with the IC arena.Al-metallization requires special attention due to its wide usage in logic and memory circuits. Logic requirements drive technology toward improved circuit performance while memory improvements require high device and wiring densities. As the dynamic random access memory (DRAM) evolves from 64 Mbits to 256 Mbits, ultralarge-scale integrated (ULSI) wiring will decrease to below sub-0.3 μm in dimensions. Such circuits require robust, reliable back end of the line (BEOL) technology that meets high-performance, low-cost, stringent electromigration requirements. We feel that several of these emerging interconnect fabrication techniques have reached a sufficient level of maturity to warrant a reasonable exposition. We will concentrate on metallization systems in this issue, leaving a discussion of dielectrics for the future, due to space limitations.The semiconductor industry has relied on aluminum technology since the 1960s because it is a well-established, low-cost technology. Early improvements in the electromigration resistance of Al lines by the addition of Cu impurities after 1971 helped this metallurgy to endure further feature size reductions, without degradation of reliability. However, the relentless reduction in via and line size once again may bring into question the limitation of Al reliability. As a result, work on alternate low-resistivity and high-electromigration-resistant metals like Cu is continuing in parallel.

Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly)

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000123-000128
Author(s):  
Erick M. Spory
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Value Added ◽  
Electroless Nickel ◽  
High Volume ◽  
Gold Plating ◽  
Global Circuit ◽  
Temperature Applications

There is an ever-increasing demand for electronics in higher temperature applications, both in variety and volume. In many cases, the actual integrated circuit within the plastic packaging can support operation at higher temperatures, although the packaging and connectivity is unable to do so. Ultimately, there still remains a significant gap in the volume demand required for high temperature integrated circuit lines to justify support of more expensive ceramic solutions by the original component manufacturer vs. the cheaper, high-volume PEM flows. Global Circuit Innovations, Inc. has developed a manufacturable, cost-effective solution to extract the integrated circuit from any plastic encapsulated device and subsequently re-package that device into an identical ceramic footprint, with the ability to maintain high-integrity connectivity to the device and enabling functionality for 1000's of hours at temperatures at 250C and beyond. This process represents a high-value added solution to provide high-temperature integrated circuits for a large spectrum of requirements: low-volume, quick-turn evaluation of integrated circuit prototyping, as well as medium to high-volume production needs for ongoing production needs. Although both die extraction and integrated circuit pad electroless nickel/gold plating have both been performed successfully for many years in the semiconductor industry, Global Circuit Innovations, Inc. has been able to combine the two in a reliable, volume manufacturing flow to satisfy many of the stringent requirements for high-temperature applications.

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Photolithography Alignment Mark Transfer System for Low Cost, Advanced Packaging, and Bonded Wafer Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001302-001327 ◽  
Author(s):  
Tom Swarbrick ◽  
Keith Best ◽  
Casey Donaher ◽  
Steve Gardner
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm has presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. And in the very cost sensitive advanced packaging arena, Outsourced Semiconductor Assembly and Test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from the backend processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, where the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with Infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist is then stripped and cleaned. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2um is readily achievable, with no impact on system throughput.

Stitch Bonding Strength of Cu Wire on AuAg/Pd/Ni Preplated Cu Leadframes: Influence of AuAg Thickness

2015 ◽  
Vol 761 ◽  
pp. 364-368 ◽  
Author(s):  
Sock Chien Tey ◽  
Kok Tee Lau ◽  
Mohd Hafizul Mohamad Noor ◽  
Yon Loong Tham ◽  
Mohd Edeerozey Abd Manaf
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Diffusion Mechanism ◽  
High Hardness ◽  
Wire Bonding ◽  
Automotive Application ◽  
Tin Whisker ◽  
Bonding Property ◽  
Ic Packaging

Copper (Cu) wire bonding on the pre-plated leadframes with Ni/Pd/AuAg plating has been applied extensively in the semiconductor industry for the interconnection of integrated-circuit (IC) packaging due to the lower material cost of Cu and its excellent electrical properties. Furthermore, the Cu wire bonding on the preplated leadframe has advantages, such as the tin whisker prevention and the robust package for automotive application. Nevertheless, a stitch bondability of Cu wire-preplated leadframe is facing several challenges, such as the Cu oxidation, the high hardness of Cu wire and the very thin AuAg plating on the leadframes. This paper discusses the effect of AuAg plating thickness in roughened pre-plated leadframe on the stitch bonding of Cu wires with the leadframe. The stitch bonding integrity was assessed using Dage 4000 shear/pull tool at a key wire bond responses of stitch pull at time zero (T0). Results show that the stitch pull strength of the Cu-leadframe stitch bonding increases with the increase thickness of AuAg layer. FESEM images of the stitch bonding between the Cu wires and the pre-plated leadframes of different AuAg plating thickness did not show any defect in microstructures, thus it suggests that the bonding property is determined by diffusion mechanism at the Cu wire/AuAg stitch bonding interface. Finally, a brief discussion is provided on the stitch bondability of high performance Au-flashed palladium-coated copper wires on the pre-plated leadframe with different AuAg thickness.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

scholarly journals Open innovation in the semiconductor industry: analysis of Brazilian design houses

2019 ◽  
Vol 17 (2) ◽  
pp. 133-156
Author(s):  
Xênia L'amour Campos Oliveira ◽  
Maria Elena Leon Olave ◽  
Edward David Moreno ◽  
Glessia Silva
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Open Innovation ◽  
Semiconductor Industry ◽  
Innovation Process ◽  
Research Strategy ◽  
Structured Interviews ◽  
Content Type ◽  
New Business ◽  
Multiple Case

Purpose This study aims to understand how Brazilian design houses (DHs) use open innovation in joint development projects for integrated circuits. Design/methodology/approach As a research strategy, qualitative research using multiple case studies was made. As sources of evidence, semi-structured interviews were conducted with three DHs of Programa integrated circuit [circuito integrado(CI)]-Brasil and with four specialists in the field, as well as analysis of documents. The data were analyzed through content analysis. Findings The results showed the DHs use sources of external knowledge in their innovation process, to assist the development of new products, to access new knowledge and skills, to attract financial resources and to be competitive in the market of high technology. Originality/value The study has important implications on the semiconductor industry in Brazil, as the industry is considered strategic for the competitiveness of final goods sector. The importance of encouraging the development of partnerships in the sector, the possibility of using informal agreements to mediate the collaboration between DHs and external agents, and the improvement and long-term continuity of public policies to support the industry are among the implications. In addition to suggestions for new business approaches to assist the strengthening of this segment.

Adaptive Hot-Spot Cooling of Integrated Circuits Using Digital Microfluidics

2005 ◽  
Author(s):  
Phil Paik ◽  
Vamsee K. Pamula ◽  
Krishnendu Chakrabarty
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
High Performance ◽  
Cooling System ◽  
Hot Spot ◽  
Digital Microfluidics ◽  
Ic Design ◽  
Spot Cooling ◽  
Digital Microfluidic

Thermal management is becoming an increasingly important issue in integrated circuit (IC) design. The ability to cool ICs is quickly reaching a limit with today’s package-level solutions. While a number of novel cooling methods have been introduced, many of which are microfluidic approaches, these methods are unable to adaptively address the uneven thermal profiles and hot-spots generated in high performance ICs. In this paper, we present a droplet-based digital microfluidic cooling system for ICs that can adaptively cool hot-spots through real-time reprogrammable flow. This paper characterizes the effectiveness of microliter-sized droplets for cooling by determining the heat transfer coefficient of a droplet shuttling back and forth in an open system over a hot-spot at various speeds. Cooling is found to be significantly enhanced at higher flow rates of droplets. In order to further enhance cooling, the effect of varying droplet aspect ratio (width/height) in a confined system was also studied.

scholarly journals Inch-sized high-quality perovskite single crystals by suppressing phase segregation for light-powered integrated circuits

2021 ◽  
Vol 7 (7) ◽  
pp. eabc8844
Author(s):  
Yucheng Liu ◽  
Yunxia Zhang ◽  
Xuejie Zhu ◽  
Zhou Yang ◽  
Weijun Ke ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Single Crystals ◽  
Integrated Circuit ◽  
High Performance ◽  
Imaging System ◽  
Phase Segregation ◽  
Response Speed ◽  
Fast Response ◽  
High Quality ◽  
Carrier Lifetimes

The triple-cation mixed-halide perovskite (FAxMAyCs1-x-y)Pb(IzBr1-z)3 (FAMACs) is the best composition for thin-film solar cells. Unfortunately, there is no effective method to prepare large single crystals (SCs) for more advanced applications. Here, we report an effective additive strategy to grow 2-inch-sized high-quality FAMACs SCs. It is found that the judiciously selected reductant [formic acid (FAH)] effectively minimizes iodide oxidation and cation deprotonation responsible for phase segregation. Consequently, the FAMACs SC shows more than fivefold enhancement in carrier lifetimes, high charge mobility, long carrier diffusion distance, as well as superior uniformity and long-term stability, making it possible for us to design high-performance self-powered integrated circuit photodetector. The device exhibits large responsivity, high photoconductive gain, excellent detectivity, and fast response speed; all values are among the highest reported to date for planar-type single-crystalline perovskite photodetectors. Furthermore, an integrated imaging system is fabricated on the basis of 12 × 12 pixelated matrixes of the single-crystal photodetectors.

PHOTOLITHOGRAPHY ALIGNMENT MARK TRANSFER SYSTEM FOR LOW COST ADVANCED PACKAGING AND BONDED WAFER APPLICATIONS

2016 ◽  
Vol 2016 (1) ◽  
pp. 000315-000320 ◽  
Author(s):  
Keith Best ◽  
Steve Gardner ◽  
Casey Donaher
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Abstract Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm have presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. In this very cost sensitive advanced packaging arena, outsourced semiconductor assembly and test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from back-end processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, that the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist stripped, and the lithography layer reworked. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper-based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2μm is readily achievable, with no impact on system throughput.

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