Mechanics of Direct Wafer Bonding

2003 ◽  
Author(s):  
K. T. Turner ◽  
S. M. Spearing
Keyword(s):  
Wafer Bonding ◽  
Microelectromechanical Systems ◽  
Surface Condition ◽  
Bonding Process ◽  
Mems Devices ◽  
Wafer Level ◽  
Modeling Framework ◽  
Etch Patterns ◽  
Direct Wafer Bonding ◽  
Bonding Failure

Direct wafer bonding, also known as fusion bonding, has emerged as a key process in the manufacture of microelectromechanical systems (MEMS). The use of wafer bonding increases design flexibility, allows integration of dissimilar materials, and permits wafer-level packaging. While direct wafer bonding processes are becoming more prevalent in the fabrication of MEMS devices, failure during the bonding process is often a problem and is not completely understood. A modeling framework, based on the mechanics of the bonding process, has been on the mechanics of the bonding process, has been developed to correlate bonding failure to wafer geometry, surface condition, and etch patterns. The modeling approach is based on an energy balance between the reduction in surface energy as the bond is formed and the strain energy that is stored in the wafers as they conform to each other. The model allows the effect of flatness deviations, wafer geometry (i.e. thickness, diameter), wafer mounting, and etched features on the bonding process to be shown. Modeling results demonstrate that wafer bow, wafer thickness, and certain types of etch patterns are critical factors in controlling bonding success. Bonding experiments, in which specific flatness deviations and etch patterns have been introduced on wafers prior to bonding, have been carried out and compared to the modeling results. The understanding of the process gained through the modeling can be used to set tolerances on wafers, assist in mask layout, and guide the design of bonding equipment to ensure success in direct wafer bonding processes.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Microsensors, MEMS and NEMS Based Complex Adaptive Smart Devices and Systems

2001 ◽  
Author(s):  
Vijay K. Varadan
Keyword(s):  
Self Assembly ◽  
Communication Systems ◽  
Microelectromechanical Systems ◽  
System Level ◽  
Smart Devices ◽  
Mems Devices ◽  
Wafer Level ◽  
Sensors And Actuators ◽  
Complex Adaptive ◽  
Microelectronics Industry

Abstract The microelectronics industry has seen explosive growth during the last thirty years. Extremely large markets for logic and memory devices have driven the development of new materials, and technologies for the fabrication of even more complex devices with features sizes now down at the sub micron level. Recent interest has arisen in employing these materials, tools and technologies for the fabrication of miniature sensors and actuators and their integration with electronic circuits to produce smart devices and MicroElectroMechanical Systems (MEMS). This effort offers the promise of: 1. Increasing the performance and manufacturability of both sensors and actuators by exploiting new batch fabrication processes developed for the IC and microelectronics industry. Examples include micro stereo lithographic and micro molding techniques. 2. Developing novel classes of materials and mechanical structures not possible previously, such as diamond like carbon, silicon carbide and carbon nanotubes, micro-turbines and micro-engines. 3. Development of technologies for the system level and wafer level integration of micro components at the nanometer precision, such as self-assembly techniques and robotic manipulation. 4. Development of control and communication systems for MEMS devices, such as optical and RF wireless, and power delivery systems.

Characterization of Wafer Level Metal Thermo-Compression Bonding

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002326-002360
Author(s):  
Erkan Cakmak ◽  
Bioh Kim ◽  
Viorel Dragoi
Keyword(s):  
Surface Treatment ◽  
Metal Surface ◽  
Bonding Temperature ◽  
Transient Liquid Phase ◽  
Bonding Process ◽  
Bending Test ◽  
Strength Analysis ◽  
Mems Devices ◽  
Wafer Level ◽  
Bond Quality

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB. In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test. Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system. To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Wafer-Level Strength and Fracture Toughness Testing of Surface-Micromachined MEMS Devices

1999 ◽  
Vol 605 ◽  
Author(s):  
H. Kahn ◽  
N. Tayebi ◽  
R. Ballarini ◽  
R.L. Mullen ◽  
A.H. Heuer
Keyword(s):  
Fracture Toughness ◽  
Tensile Strength ◽  
Microelectromechanical Systems ◽  
Reliability Prediction ◽  
Bend Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Toughness Testing ◽  
Loading Devices

AbstractDetermination of the mechanical properties of MEMS (microelectromechanical systems) materials is necessary for accurate device design and reliability prediction. This is most unambiguously performed using MEMS-fabricated test specimens and MEMS loading devices. We describe here a wafer-level technique for measuring the bend strength, fracture toughness, and tensile strength of MEMS materials. The bend strengths of surface-micromachined polysilicon, amorphous silicon, and polycrystalline 3C SiC are 5.1±1.0, 10.1±2.0, and 9.0±1.0 GPa, respectively. The fracture toughness of undoped and P-doped polysilicon is 1.2±0.2 MPa√m, and the tensile strength of polycrystalline 3C SiC is 3.2±1.2 GPa. These results include the first report of the mechanical strength of micromachined polycrystalline 3C SiC.

Study on Anodic Bonding Process of Slender Vitreous Body

2012 ◽  
Vol 503 ◽  
pp. 435-439
Author(s):  
Ming Qiang Pan ◽  
Li Guo Chen ◽  
Tao Chen ◽  
Zhen Hua Wang ◽  
Li Ning Sun
Keyword(s):  
Body Shape ◽  
Pressure Sensors ◽  
Vitreous Body ◽  
Bonding Process ◽  
Anodic Bonding ◽  
Interface Temperature ◽  
Process Conditions ◽  
Mems Devices ◽  
Bonding Failure ◽  
Mems Technology

With the development of MEMS technology, the pressure sensors, one of mature MEMS devices, are expected to better performance. In order to improve sensors performance, supporting vitreous body shape is elongated and thinned. But the variety of the vitreous body shape brings the new difficulties for anodic bonding between the vitreous body and the silicon during the sensors production, and causes that the common bonding process conditions are unavailable and bonding failure rate dramatically increases. Therefore, this article analyzes the bonding process between slender vitreous body and silicon, and researches on the influence of the vitreous body variety on the pressure, temperature and voltage. The results showed that the bonding is the best when the cantilever elastic deformation is less than 0.5mm, interface temperature loaded from the silicon is 415°C and the voltage 1200V is loaded from the position near H=2mm.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Seebeck Coefficient of Ge-on-Insulator Layers Fabricated by Direct Wafer Bonding Process

2015 ◽  
Vol 1117 ◽  
pp. 94-97 ◽  
Author(s):  
Veerappan Manimuthu ◽  
Shoma Yoshida ◽  
Yuhei Suzuki ◽  
Faiz Salleh ◽  
Mukannan Arivanandhan ◽  
...  
Keyword(s):  
Seebeck Coefficient ◽  
Wafer Bonding ◽  
Annealing Effect ◽  
Bonding Process ◽  
Infrared Photodetector ◽  
Si Substrate ◽  
Temperature Range ◽  
Direct Wafer Bonding ◽  
Insulator Layers ◽  
P Type

We investigate thermoelectric characteristics of SiGe nanostructures for realizing high-sensitive infrared photodetector applications. In this paper, for future Ge and SiGe nanowires, we fabricate p-type Ge-on-insulator (GOI) substrates by a direct wafer bonding process. We discuss the annealing effect on the GOI substrate in the process and measure its Seebeck coefficient in the temperature range of 290-350 K. The Seebeck coefficient of the GOI layers is almost identical with the reported values for Ge. This result confirms that the measured Seebeck coefficient of GOI layers is not influenced by the buried oxide (BOX) layer and the Si substrate.

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