INTRODUCTION TO LOW-POWER VLSI DESIGN

1996 ◽  
Vol 07 (02) ◽  
pp. 223-248 ◽  
Author(s):  
GARY YEAP ◽  
ANDREAS WILD
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Ad Hoc ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Low Power Design ◽  
Current Status ◽  
Trade Offs ◽  
Device Structures ◽  
The Impact

The paper is a survey of the current status of research and practices in various disciplines of low-power VLSI developments. After briefly discussing the rationale of the contemporary focus on low-power design, it presents the metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency. The requirements to be fulfilled by process technologies and device structures are reviewed as well as several promising circuit design styles and ad hoc design techniques. The impact of the design automation tools is analyzed with a special emphasis on physical design and logic synthesis. A review of various architectural trade-offs, including power management, parallelism and pipelining, synchronous versus asynchronous architectures and dataflow transformations are covered, followed by a brief discussion of the impact of the system definition, software and algorithms to the overall power efficiency. Emerging semiconductor technologies and device structures are discussed and the paper is concluded with the trends and research topics for the future.

Low-power design tools---where is the impact? (panel)

1997 ◽  
Author(s):  
Jan M. Rabaey ◽  
Nanette Collins ◽  
Bill Bell ◽  
Jerry Frenkil ◽  
Vassilios Gerousis ◽  
...  
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Tools ◽  
The Impact

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

Contemporary Low Power Design Approaches

2016 ◽  
pp. 101-127
Author(s):  
Lini Lee
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
Cmos Technology ◽  
Simulation Tool ◽  
Bandgap Reference ◽  
Voltage Level ◽  
Dynamic Comparator ◽  
Reference Circuit ◽  
Level Shifter

This chapter describes three contemporary low power design approaches; a resistor-less bandgap reference circuit, a hybrid voltage level shifter with a diode connected NMOS and a modified dynamic comparator, each design with the objective to demonstrate the feasibility of contemporary approaches in achieving lower power VLSI design. All three designs are simulated in 0.18 µm CMOS technology using industrial simulation tool and the results are based on performance parameters defined in the chapter.

CHARACTERIZATION, TEST AND LOGIC SYNTHESIS OF NOVEL CONSERVATIVE AND REVERSIBLE LOGIC GATES FOR QCA

2010 ◽  
Vol 09 (03) ◽  
pp. 201-214 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Logic Gates ◽  
Reversible Logic ◽  
Computing Paradigm ◽  
Scale Integration

Quantum dot cellular automaton (QCA) is an emerging technology in the field of nanotechnology. Reversible logic is emerging as a promising computing paradigm with applications in low-power quantum computing and QCA in the field of very large scale integration (VLSI) design. In this paper, we worked on conservative logic gate (CLG) and reversible logic gate (RLG). We examined that RLG and CLG are two classes of logic family intersecting each other. The intersection of RLG and CLG is parity preserving reversible (PPR) or conservative reversible logic gate (CRLG). We proposed in this paper, three algorithms to find different k × k RLG as well as CLG. Here, we demonstrate only the most promising two proposed gates of different categories. We compared the results with that of the previous Fredkin gate. The result shows that logic synthesis using above two gates will be a promising step towards the low-power QCA design era. We have shown a parity preserving approach to design all possible CLG. We also discuss a coupled Majority–minority-Voter (MmV) in a single nanostructure, dual outputs are driven simultaneously. This MmV gate is used for implementing n variables symmetric functions, testing the conservative gates as we explained that parity must be preserved if Majority and Minority output are same as input as well as output of CLG.

scholarly journals DESIGN &ANALYSIS OF DUAL STACK METHOD FOR FUTURE TECHNOLOGIES

2015 ◽  
pp. 245-250
Author(s):  
P. RAVALI TEJA ◽  
D. AJAY KUMAR
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Vlsi Design ◽  
Design Analysis ◽  
Leakage Power ◽  
Power Gating ◽  
Comparison Results ◽  
Different Types ◽  
Low Power Vlsi Design ◽  
Future Technologies

As low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly so for removing these kind of leakages and to provide a better power efficiency we are using many types of power gating techniques. In this paper we are going to analyse the different types of flip-flops using different types of power gated circuits using low power VLSI design techniques and we are going to display the comparison results between different nanometer technologies. The NMOS1mulations were done using Microwind Layout Editor & DSCH software and the results were given below.

scholarly journals Analysis of the Soiling Effect on Solar-Panel Power Efficiency in the Colombian Caribbean Region

2019 ◽  
Author(s):  
Juan David Diazgranados-Garzón ◽  
Juan Camilo Romero-Bravo ◽  
Loraine Isabel Navarro-Estrada ◽  
Rafael De Jesús Castillo-Sierra ◽  
Jose Daniel Soto-Ortiz ◽  
...  
Keyword(s):  
Solar Radiation ◽  
Electric Power ◽  
Power Efficiency ◽  
Particulate Material ◽  
Solar Panel ◽  
Caribbean Region ◽  
Particle Accumulation ◽  
Trade Offs ◽  
The Times ◽  
The Impact

This paper summarizes the impact of particulate material on solar-panel performance for systems located in the Colombian Caribbean Region. First, the dirt/particles are identified and classified; and then, their effect in the reduction of solar panel efficiency has been estimated at most of 6% during the times of the day with the maximum solar radiation. It has been found that the impact decreases exponentially for other hours during the day, which implies that dirt effect becomes negligible on the electric power available. The study reveals that the effect of dirt/particles is significant from a clean solar panel to one with light accumulation, but rapidly diminishes as accumulation changes from light to heavy. Thus, it is suggested that once some dirt accumulates on the panel, a cleaning procedure can wait until the particle accumulation is heavy without sacrificing efficiency excessively. The results of the study become a tool to estimate the trade-offs between power efficiency of photovoltaic systems and financial viability of those projects. Hence, inverters can be chosen such that they can limit the amount of electric power while minimizing the stochastic nature of solar radiation and the dirt/particle effect. The analysis presented starts through a complete Multivariate Analysis of Variance (ANOVA) considering three fundamental factors: dirt/particles, solar radiation and day.

A Survey on Low Power Design Approaches in nanoscale regime

2020 ◽  
Vol 12 ◽  
Author(s):  
Vijay Kumar Sharma
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Vlsi Design ◽  
Low Power Design ◽  
Technology Node ◽  
Reduction Techniques ◽  
The Individual ◽  
Technology Nodes

Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3-input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and improving the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

scholarly journals SmarTEG: An Autonomous Wireless Sensor Node for High Accuracy Accelerometer-Based Monitoring

Sensors ◽  
2019 ◽  
Vol 19 (12) ◽  
pp. 2747 ◽  
Author(s):  
Michele Magno ◽  
Lukas Sigrist ◽  
Andres Gomez ◽  
Lukas Cavigelli ◽  
Antonio Libri ◽  
...  
Keyword(s):  
Low Power ◽  
Thermoelectric Generator ◽  
Low Power Design ◽  
Low Complexity ◽  
High Accuracy ◽  
Sensor Data ◽  
Field Energy ◽  
Wireless Sensor Node ◽  
Ultra Low Power ◽  
The Impact

We report on a self-sustainable, wireless accelerometer-based system for wear detection in a band saw blade. Due to the combination of low power hardware design, thermal energy harvesting with a small thermoelectric generator (TEG), an ultra-low power wake-up radio, power management and the low complexity algorithm implemented, our solution works perpetually while also achieving high accuracy. The onboard algorithm processes sensor data, extracts features, performs the classification needed for the blade’s wear detection, and sends the report wirelessly. Experimental results in a real-world deployment scenario demonstrate that its accuracy is comparable to state-of-the-art algorithms executed on a PC and show the energy-neutrality of the solution using a small thermoelectric generator to harvest energy. The impact of various low-power techniques implemented on the node is analyzed, highlighting the benefits of onboard processing, the nano-power wake-up radio, and the combination of harvesting and low power design. Finally, accurate in-field energy intake measurements, coupled with simulations, demonstrate that the proposed approach is energy autonomous and can work perpetually.

A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging

2020 ◽  
Vol 10 (4) ◽  
pp. 814-821
Author(s):  
J. Sureshbabu ◽  
G. Saravanakumar
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Power Dissipation ◽  
Power Efficiency ◽  
High Speed ◽  
Average Power ◽  
Vlsi Design ◽  
Propagation Time ◽  
Power Gating ◽  
Booth Multiplier

In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagation time delay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplier's immensity. It increases the accuracy and reduces complexity through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. To solve this problem, the proposed system is designed with a power gating based 16 × 16 bit Booth multiplier based on approximate recoding adder. It decreases the power dissipation and minimizes the length and width of the partial products for speeding up the multiplication process. The results obtained from the simulation show that the designed power gating based Radix multiplier circuits achieves better PDP, average power and area. The achieved results are compared with a Radix based multiplier, power gating CLA based multiplier and CLA based multiplier.

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