Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

2019 ◽  
Vol 28 (12) ◽  
pp. 1950197 ◽  
Author(s):  
Anjali Sharma ◽  
Harsh Sohal ◽  
Harsimran Jit Kaur
Keyword(s):  
Circuit Design ◽  
Power Efficiency ◽  
High Speed ◽  
Total Power ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Power Efficient ◽  
Area Product ◽  
Power Delay Product ◽  
Very High

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

scholarly journals Design and Implementation of Power-Efficient FSM based UART

2022 ◽  
Vol 2161 (1) ◽  
pp. 012052
Author(s):  
Akshatha Kamath ◽  
Tanya Mendez ◽  
S Ramya ◽  
Subramanya G Nayak
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Total Power ◽  
Clock Frequency ◽  
General Process ◽  
Baud Rate ◽  
Power Efficient ◽  
Vlsi Chip ◽  
Finite State ◽  
Power Delay Product

Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

scholarly journals Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

2019 ◽  
Vol 9 (1) ◽  
pp. 4340-4347
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Digital Design ◽  
Total Power ◽  
Power Comparison ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Area Efficiency ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

ANALYSIS OF A NOVEL FULL ADDER DESIGNED FOR IMPLEMENTING IN CARBONE NANOTUBE TECHNOLOGY

2012 ◽  
Vol 21 (05) ◽  
pp. 1250042 ◽  
Author(s):  
MAHDIAR GHADIRY ◽  
MAHDIEH NADI ◽  
HOSEIN MOHAMMADI ◽  
ASRULNIZAM BIN ABD MANAF
Keyword(s):  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Ultra Low Power ◽  
New Approach ◽  
And Performance ◽  
Carbon Nanotube Technology ◽  
Power Delay Product ◽  
Full Swing ◽  
Very High

A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advantages of using carbon-based transistors in digital designs over conventional silicon technology. The proposed circuit can be applied in ultra low power and very high speed applications.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

An Analysis of Power Characteristics of Oil-Free Scroll Vacuum Pumps

2020 ◽  
pp. 37-43
Author(s):  
A.V. Tyurin ◽  
A.V. Burmistrov ◽  
A.A. Raykov ◽  
S.I. Salikeev
Keyword(s):  
Mathematical Model ◽  
Power Efficiency ◽  
High Speed ◽  
Pressure Sensors ◽  
Operating Conditions ◽  
Total Power ◽  
Radial Clearance ◽  
Geometrical Parameters ◽  
Power Characteristics ◽  
Indicator Power

This paper presents an analysis of the indicator power of an oil-free scroll vacuum pump based on the indicator diagrams obtained through high-speed pressure sensors. These values are compared with the results of calculations using a mathematical model of the pump working process. It is shown that the divergence of the calculated results and experimental values does not exceed 4%, which confirms the adequacy of the developed mathematical model. The total power of the scroll pump exceeds the indicator power by more than 2 times due to the friction losses between the face seals and disks of the reciprocal scroll elements, friction losses in the stuffing box seals and rolling bearings, as well as due to the coefficient of efficiency of the motor. The influence of the radial clearance between the scroll elements on the power consumption is considered. It is shown that at low pressures nearing the ultimate pressure, the power increases with the increased clearance, while at inlet pressures exceeding 40 kPa it decreases. The performed analysis can be used for selecting the optimal geometrical parameters of the scroll elements and increasing power efficiency of the pump depending on specific operating conditions.

scholarly journals Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

2022 ◽  
Vol 2161 (1) ◽  
pp. 012050
Author(s):  
Imran Ahmed Khan
Keyword(s):  
High Speed ◽  
Full Adder ◽  
Logic Circuits ◽  
Power Efficient ◽  
Cmos Transistors ◽  
Bases Of Power ◽  
Ripple Carry Adder ◽  
Supply Voltages ◽  
Power Delay Product ◽  
Carbon Nano Tube

Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

Design of low power and high speed implicit pulse flip-flop and its application

2018 ◽  
Vol 7 (3) ◽  
pp. 1893 ◽  
Author(s):  
Kuruvilla John ◽  
Vinod Kumar R S ◽  
Kumar S S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Product Performance ◽  
Power Performance ◽  
Flip Flop ◽  
Power Efficient ◽  
Pass Transistor ◽  
Simulation Results ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.  

ON THE POWER EFFICIENCY OF CASCODE COMPENSATION OVER MILLER COMPENSATION IN TWO-STAGE OPERATIONAL AMPLIFIERS

2008 ◽  
Vol 17 (01) ◽  
pp. 1-13 ◽  
Author(s):  
HAMED AMINZADEH ◽  
REZA LOTFI
Keyword(s):  
Integrated Circuits ◽  
Power Efficiency ◽  
High Speed ◽  
Point Of View ◽  
Operational Amplifiers ◽  
Two Stage ◽  
Power Efficient ◽  
Miller Compensation ◽  
Function Zeros ◽  
Design Challenges

Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely, Miller and cascode compensations are compared from power efficiency point of view. To accomplish this, cascode-compensated topologies are basically analyzed to derive the required equations for the comparison. In the analysis, a new method to take into account the effect of transfer function zeros is proposed. By assuming that the zeros' magnitudes are fairly nondominant, the method increases the accuracy of the analyses. The relationships show that for the same specifications, cascode compensation is more power-efficient than Miller compensation, especially for heavy capacitive loads. This has been confirmed by SPICE simulations.

PRESENT AND FUTURE OF HIGH-SPEED COMPOUND SEMICONDUCTOR IC's

2003 ◽  
Vol 13 (01) ◽  
pp. 1-25 ◽  
Author(s):  
TAIICHI OTSUJI
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Electronic Device ◽  
State Of The Art ◽  
Compound Semiconductor ◽  
Limiting Factors ◽  
Future Trends ◽  
Communications Systems ◽  
Very High ◽  
Device Technology

This paper describes state-of-the-art of high-speed electronic device and IC technologies for very high-speed lightwave communications systems. The technology of interest is for over 40-Gbit/s transmitter and receiver operations. Device technology including Si-Ge, GaAs-based, and InP-based heterostructure transistors as well as circuit design technology including analog/digital/mixed-signal and optoelectronic IC's are reviewed. The speed limiting factors are discussed to address the future trends toward 100 Gbit/s and beyond.

Sign in / Sign up

Export Citation Format

Share Document