ANALOG DENDRO-DENDRITIC ARRAYS WITH DIGITAL ON-CHIP LEARNING

1998 ◽  
Vol 08 (05n06) ◽  
pp. 571-587
Author(s):  
F. M. SALAM ◽  
Y. WANG ◽  
G. ERTEN
Keyword(s):  
Power Dissipation ◽  
Building Blocks ◽  
Cmos Technology ◽  
Digital Learning ◽  
Chip Design ◽  
Learning Capability ◽  
Chip Size ◽  
On Chip ◽  
Digital Circuitry ◽  
Fully Connected

A design of arrays of CMOS analog Dendro-dendritic Artificial Neural Network (DANN) chips with on-chip digital learning is described. The building blocks, namely, the neuron unit and the adaptive synapse, are employed to construct several architectures. One design comprises a reconfigurable fully-connected array chip integrating 50-neurons. A second array chip design integrates (9×9=81) neuron units and 825 locally-connected reconfigurable weights. In all cases, a connection is realized as a single (nonlinear) transistor with adaptive digital circuitry. The chip is designed and fabricated in 6.8 mm× 4.6 mm chip size using 2 μm CMOS technology. As an example of an application of the fabricated dendro-dendritic neural chips, real-time experiments are described in which the chips are used as a parallel digital coprocessor to demonstrate their applicability as pattern associators. These experiments entail learning an arbitrary binary image in about 10 ns with guaranteed learning capability. The stored image can subsequently be retrieved by images distorted by binary-noise in the order of 100 ns. The power dissipation of these chips in steady state is less than 5 mW using 0/5 V power supply.

scholarly journals Approximate Adder: Lower-Part or Adder

2020 ◽  
Vol 9 (7) ◽  
pp. 1176-1180
Keyword(s):  
Real Time ◽  
Power Dissipation ◽  
High Performance ◽  
Building Blocks ◽  
Cmos Technology ◽  
Approximate Computing ◽  
Computing Technique ◽  
Ripple Carry Adder ◽  
Real Time Applications ◽  
Dsp Systems

High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy. These approximate circuits are used in error-tolerant applications, where output need not be accurate. This paper concentrates mainly on approximate adders, as they are major building blocks of DSP systems. The analysis of the Lower-part OR Adder for 4-bit addition and comparison of it with the precise adder i.e., Ripple Carry Adder using the mentor graphics tool in 90 nm CMOS technology are presented in this paper. Our experimental results show that there is 17%-70% savings in power dissipation, 4%-32% saving in the area, and 19%-84% savings in time due to approximate adder. As the LOA-2 and LOA-3 are performing optimally these two adders can be used for error-tolerant applications and based on the requirement LOA-2 or LOA-3 can be selected.

scholarly journals A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1210
Author(s):  
Hanh Dang-ba ◽  
Gyung-su Byun
Keyword(s):  
Wireless Power Transfer ◽  
Cmos Technology ◽  
Power Delivery ◽  
Transfer Efficiency ◽  
Power Transfer ◽  
Wireless Power ◽  
Wafer Level ◽  
Power Transfer Efficiency ◽  
Chip Size ◽  
On Chip

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

scholarly journals Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 15 ◽  
pp. 240-248
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

Estimation of Power Density in VLSI Circuits Using Monte Carlo Simulation

1999 ◽  
Author(s):  
Mario Valenti ◽  
Z. J. Delalic ◽  
S. Jahanian
Keyword(s):  
Power Distribution ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Heat Propagation ◽  
Vlsi Circuits ◽  
Actual Distribution ◽  
3 Dimensional ◽  
Device Scaling ◽  
Circuit Components ◽  
On Chip

Abstract CMOS technology in the past twenty years has followed the path of device scaling for achieving density, speed, and power improvements. The advancement of lithographic techniques propelled the scaling also of the fine lines to 1 urn width and below. Since the integration density on chip level is constantly increasing there is need to study power dissipation and resulting heat propagation between circuit components. This research studies different methods to analyze the power dissipations and temperature distributions of a full CMOS adder. Through examining many methods, STEPS method was selected for determination of the power dissipation in a VLSI CMOS chip. An experiment was developed for the dynamic power dissipation since static power dissipation is negligible in case of CMOS devices. Using this method one can look at each circuit node individually as signals are propagated through the chip and determine power distribution in the form of heat. Therefore, it is possible to construct a 3-dimensional diagram of the actual distribution of the heat across the chip.

AN IMPROVED ELEMENTARY PROCESSING UNIT FOR HIGH-DENSITY CNN-BASED MIXED-SIGNAL MICROPROCESSORS FOR VISION

2003 ◽  
Vol 12 (06) ◽  
pp. 675-690
Author(s):  
G. LIÑÁN-CEMBRANO ◽  
S. ESPEJO ◽  
R. DOMÍNGUEZ-CASTRO ◽  
A. RODRÍGUEZ-VÁZQUEZ
Keyword(s):  
Focal Plane ◽  
Building Blocks ◽  
Cmos Technology ◽  
High Density ◽  
Processing Unit ◽  
Digital Interface ◽  
Mixed Signal ◽  
On Chip

This paper presents the architecture of the Elementary Processing Unit — EPU — which has been employed to design a CNN-Based 128×128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3×3 convolution masks,1 or information propagative CNN templates.2 Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128×128 EPUs and a completely digital interface, in a standard fully-digital 0.35 μm CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm2 and 100 GOP/J.

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

2009 ◽  
Vol 17 (9) ◽  
pp. 1267-1274 ◽  
Author(s):  
Liang Zhang ◽  
John M. Wilson ◽  
Rizwan Bashirullah ◽  
Lei Luo ◽  
Jian Xu ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Delay ◽  
Crosstalk Noise ◽  
High Data ◽  
On Chip ◽  
Bus Architecture

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

scholarly journals A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 19 ◽  
pp. 311-319
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed, Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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