Design and implementation of low-power CMOS biosignal amplifier for active electrode in biomedical application using subthreshold biasing strategy

2019 ◽  
Vol 18 (01) ◽  
pp. 1941017
Author(s):  
G. Kalpana ◽  
Raja Krishnamoorthy ◽  
P. T. Kalaivaani
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Digital Signal Processor ◽  
Biomedical Application ◽  
Research Work ◽  
Cmos Technology ◽  
Motion Artifacts ◽  
Skin Impedance ◽  
Cochlear Prosthesis ◽  
Active Electrode

Active Electrodes (AEs) are electrodes which have integrated bio-amplifier circuitry and are known to be less susceptible to motion artifacts and environmental interference. In this work, a low-power and high-input impedance amplifier for active electrode application is implemented based on subthreshold biasing strategies. In this proposed Application Specific Integrated Circuit (ASIC) device was versatile and numerical to achieve a high degree of programmability. It could be adapted to any other external part of one cochlear prosthesis, the sound analyzer that could be driven by a Digital Signal Processor (DSP). This research work also discusses the measurement of the electrode-skin impedance mismatch between two electrodes while concurrently measuring a bioelectrical signal without degradation of the performance of the amplifier, the efficient, noise-optimized analysis of bioelectrical signals utilizing two-wired active buffer electrodes. The reduction of power-line interference when using amplifying electrodes employing autonomous adaption of the gain of the subsequent differential amplification. The amplifier’s features include offset compensation, Common Mode Rejection Ratio (CMRR) improvement in software and a bandwidth extending down to DC. The proposed active electrode amplifier is designed using 90 nm CMOS technology. Simulation results exhibit up to the change in noise immunity and lessening in power utilization contrasted with the traditional bio-amplifier design at a similar delay.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals Design and verification of a low-power AC/DC converter

2021 ◽  
Vol 72 (2) ◽  
pp. 113-118
Author(s):  
Miroslav Potočný ◽  
Viera Stopjaková ◽  
Martin Kováč
Keyword(s):  
Low Power ◽  
Experimental Verification ◽  
Integrated Circuit ◽  
Power Efficiency ◽  
Printed Circuit Board ◽  
Cmos Technology ◽  
Circuit Board ◽  
Line Voltage ◽  
Power Domain ◽  
Available Technology

Abstract This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.

scholarly journals Sub-Milliwatt Transceiver IC for Transcutaneous Communication of an Intracortical Visual Prosthesis

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 24
Author(s):  
Adedayo Omisakin ◽  
Rob Mestrom ◽  
Georgi Radulov ◽  
Mark Bentum
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Vital Role ◽  
Visual Prosthesis ◽  
Outer Side ◽  
Test Chip ◽  
Wireless Links ◽  
Budget Analysis ◽  
Shift Keying

An intracortical visual prosthesis plays a vital role in partially restoring the faculty of sight in visually impaired people. Reliable high date rate wireless links are needed for transcutaneous communication. Such wireless communication should receive stimulation data (downlink) and send out neural recorded data (uplink). Hence, there is a need for an implanted transceiver that is low-power and delivers sufficient data rate for both uplink and downlink. In this paper, we propose an integrated circuit (IC) solution based on impulse radio ultrawideband using on-off keying modulation (OOK IR-UWB) for the uplink transmitter, and binary phase-shift keying (BPSK) with sampling and digital detection for the downlink receiver. To make the solution low-power, predominantly digital components are used in the presented transceiver test-chip. Current-controlled oscillators and an impulse generator provide tunability and complete the on-chip integration. The transceiver test-IC is fabricated in 180 nm CMOS technology and occupies only 0.0272 mm2. At 1.3 V power supply, only 0.2 mW is consumed for the BPSK receiver and 0.3 mW for the IR-UWB transmitter in the transceiver IC, while delivering 1 Mbps and 50 Mbps, respectively. Our link budget analysis shows that this test chip is suitable for intracortical integration considering the future off-chip antennas/coils transcutaneous 3–7 mm communication with the outer side. Hence, our work will enable realistic wireless links for the intracortical visual prosthesis.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

Small area, low power neural recording integrated circuit in 130 nm CMOS technology for small mammalians

2016 ◽  
Author(s):  
Andreas Bahr ◽  
Lait Abu Saleh ◽  
Robin Hinsch ◽  
Dietmar Schroeder ◽  
Dirk Isbrandt ◽  
...  
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Small Area ◽  
Cmos Technology ◽  
Neural Recording

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Approximate arithmetic circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 183
Author(s):  
Navabharath Reddy G ◽  
Sruti Setlam ◽  
V. Prakasam ◽  
D. Kiran Kumar
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
Compressor Design ◽  
Low Power Dissipation ◽  
Human Sense ◽  
Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

scholarly journals Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications

2019 ◽  
Vol 8 (2S3) ◽  
pp. 643-647
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
High Speed ◽  
Vlsi Design ◽  
Digital Signal ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Operating Voltage ◽  
Booth Encoder ◽  
Dsp Applications

In this paper a low power and high speed 4X4 multiplier is designed using CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v

scholarly journals Yeo Kiat Seng

2020 ◽  
Author(s):  
Kiat Seng Yeo
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
University Of Technology ◽  
Founding Director ◽  
The Republic ◽  
The University ◽  
Technological University

Professor Yeo Kiat Seng received the B.Eng. (EE) in 1993, and Ph.D. (EE) in 1996 both from Nanyang Technological University (NTU), Singapore. Currently, he is Associate Provost (Research and International Relations), Singapore University of Technology and Design (SUTD). Yeo is a widely known authority in low-power RF/mm-wave IC design and a recognized expert in CMOS technology. He was a Member of Board of Advisors of the Singapore Semiconductor Industry Association. Before his appointment at SUTD, Yeo was Associate Chair (Research), Head of Division of Circuits and Systems, Sub-Dean (Student Affairs) and Founding Director of VIRTUS of the School of Electrical and Electronic Engineering at NTU. He has published 9 books, 7 book chapters, over 600 international top-tier refereed journals and conference papers and holds 38 patents. In addition, Yeo holds/held key positions in many international conferences as Advisor, General Chair, Co-General Chair and Technical Chair. In 2009, Yeo was awarded the Public Administration Medal (Bronze) on National Day 2009 by the President of the Republic of Singapore and the Nanyang Alumni Achievement Award by NTU for his outstanding contributions to the university and society. Yeo is an IEEE Fellow for his contributions to low-power integrated circuit design.

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