Review of Research on Storage Development

2021 ◽  
Vol 22 (3) ◽  
pp. 365-385
Author(s):  
Honghong Zhang ◽  
Guoguo Zhang
Keyword(s):  
Dual Space ◽  
Random Access ◽  
Development Trend ◽  
Magnetic Core ◽  
Hard Disks ◽  
Continuous Change ◽  
Access Memory ◽  
Semiconductor Memory ◽  
Core Storage ◽  
The Development Trend

The development of computer external storage has undergone the continuous change of perforated cassettes, tapes, floppy disks, hard disks, optical disks and flash disks. Internal memory has gone through the development of drum storage, Williams tube, mercury delay line, and magnetic core storage, until the emergence of semiconductor memory. Later RAM and ROM were born. RAM was divided into DRAM and SRAM. Due to its structure and cost advantages, DRAM has gradually developed into the widely used DDR series. At the same time, the low-power LPDDR series has also been advancing. At present, with the development of NVRAM technology, non-volatile random access memory with both internal and external storage functions is born. Dual-space storage based on NVRAM combines internal and external storage into one, and large capacity dual-space storage has become the development trend of storage.  

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

Design of Dynamic Random Access Memory Refresh Circuit Based on Temperature

2021 ◽  
Vol 16 (2) ◽  
pp. 235-242
Author(s):  
Wan-Jun Yin ◽  
Zheng-Feng Ming ◽  
Tao Wen ◽  
Yi-Xue Yuan
Keyword(s):  
High Temperature ◽  
Power Consumption ◽  
Random Access ◽  
Random Access Memory ◽  
Cmos Process ◽  
Access Memory ◽  
Storage Unit ◽  
The Core ◽  
Simulation Results ◽  
Core Storage

This paper proposed a temperature adaptive refresh circuit for traditional memory with fixed refresh frequency, high refresh power consumption at low temperature and low refresh frequency at high temperature. The 2T core storage unit combining with the existing CMOS process and circuit is taking as the research object, considering the characteristics of temperature rising, leakage current increasing, information holding time shortening, and the various constraints between the area, power consumption and other performance, this paper proposes to add the same redundant unit as the storage array to the storage array as the temperature monitoring circuit to realize the adaptive refresh function, and designs the core circuit. The simulation results show that the design of SMIC 0.09 um standard CMOS process fully meets the requirements of memory adaptive refresh.

scholarly journals Browsers’ Private Mode: Is It What We Were Promised?

Computers ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 165
Author(s):  
Kris Hughes ◽  
Pavlos Papadopoulos ◽  
Nikolaos Pitropakis ◽  
Adrian Smales ◽  
Jawad Ahmad ◽  
...  
Keyword(s):  
Random Access ◽  
Forensic Analysis ◽  
Test Cases ◽  
Sensitive Information ◽  
Web Browsers ◽  
Hard Disks ◽  
Access Memory ◽  
Web Browser ◽  
Left Behind ◽  
Search History

Web browsers are one of the most used applications on every computational device in our days. Hence, they play a pivotal role in any forensic investigation and help determine if nefarious or suspicious activity has occurred on that device. Our study investigates the usage of private mode and browsing artefacts within four prevalent web browsers and is focused on analyzing both hard disk and random access memory. Forensic analysis on the target device showed that using private mode matched each of the web browser vendors’ claims, such as that browsing activity, search history, cookies and temporary files that are not saved in the device’s hard disks. However, in volatile memory analysis, a majority of artefacts within the test cases were retrieved. Hence, a malicious actor performing a similar approach could potentially retrieve sensitive information left behind on the device without the user’s consent.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

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