scholarly journals Microchip Transfer Process for Implantable Flexible Bioelectronic Devices

2021 ◽  
Vol 7 (2) ◽  
pp. 41-44
Author(s):  
Julien Martens ◽  
Calogero Gueli ◽  
Max Eickenscheidt ◽  
Thomas Stieglitz

Abstract The demands on flexible implants for recording of neural signals and electrical stimulating have increased in recent years with regard to their functionality, miniaturization, and spatial resolution. These requirements can be met best by embedding powerful complementary metal oxide semiconductor (CMOS) microchips into thin biocompatible polymer substrates. So-called chip-in-foil systems thus combine mechanical properties of a polymer substrate and performance of CMOS technology. The development of a process for direct transfer of multiple CMOS microchips (edge length <400 μm) simultaneously into thin polyimide (PI) substrates is subject of this study. It allows the use of standard microelectromechanical systems (MEMS) processes for further levelled superficial layer build-up. This is achieved with the help of a silicon carrier wafer equipped with cavities for precise chip placement and a sacrificial layer to facilitate release of the chip-in-foil systems. In a post-processing step all silicon chips are thinned down to 100 μm. With this process a transfer yield of 100 % (n = 34) was achieved for the silicon chips on a die level. Chip rotational error on substrates was determined to be as low as 0.21° ± 0.10°. Die adhesion was examined by shear tests, resulting in shear strength of 58.1 MPa ± 13.7 MPa, which dropped to 15.2 MPa ± 10.5 MPa after accelerated ageing in 60 °C phosphate buffered saline solution (PBS) for 16 days (equivalent to 78 days at 37 °C). This study demonstrated a reliable microchip transfer process with low positioning error into flexible PI substrates with post-processing thinning of the dies. The use of a carrier silicon wafer allowed precise electrical interconnect fabrication with standard MEMS processing techniques and without handling of thin and fragile chips. These results are a prerequisite to meet needs of reliability and structural biocompatibility in implantable flexible bioelectronic devices.

2012 ◽  
Vol 24 (3) ◽  
pp. 310-317 ◽  
Author(s):  
Wei-Hsiang Tu ◽  
Wen-Chang Chu ◽  
Chih-Kung Lee ◽  
Pei-Zen Chang ◽  
Yuh-Chung Hu

Etching the large area of sacrificial layer under the microstructure to be released is a common method used in microelectromechanical systems technology. In order to completely release the microstructures, many etching holes are often required on the microstructure to enable the etchant to completely etch the sacrificial layer. However, the etching holes often alter the electromechanical properties of the micro devices, especially capacitive devices, because the fringe fields induced by the etching holes can significantly alter the electrical properties. This article is aimed at evaluating the fringe field capacitance caused by etching holes on microstructures. The authors aim to find a general capacitance compensation formula for the fringe capacitance of etching holes by the use of ANSYS simulation. According to the simulation results, the design of a capacitive structure with small etching holes is recommended to prevent an extreme capacitance decrease. In conclusion, this article provides a fringing field capacitance estimation method that shows the capacitance compensation tendency of the design of etching holes; this method is expected to be applicable to the design in capacitive devices of complementary metal oxide semiconductor–microelectromechanical systems technology.


2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.


Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.


1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.


Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.


Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.


2021 ◽  
Author(s):  
Akhil Dodda ◽  
Darsith Jayachandran ◽  
Shiva Subbulakshmi Radhakrishnan ◽  
Saptarshi Das

Abstract Natural intelligence has many dimensions, and in animals, learning about the environment and making behavioral changes are some of its manifestations. In primates vision plays a critical role in learning. The underlying biological neural networks contain specialized neurons and synapses which not only sense and process the visual stimuli but also learns and adapts, with remarkable energy efficiency. Forgetting also plays an active role in learning. Mimicking the adaptive neurobiological mechanisms for seeing, learning, and forgetting can, therefore, accelerate the development of artificial intelligence (AI) and bridge the massive energy gap that exists between AI and biological intelligence. Here we demonstrate a bio-inspired machine vision based on large area grown monolayer 2D phototransistor array integrated with analog, non-volatile, and programmable memory gate-stack that not only enables direct learning, and unsupervised relearning from the visual stimuli but also offers learning adaptability under photopic (bright-light), scotopic (low-light), as well as noisy illumination conditions at miniscule energy expenditure. In short, our “all-in-one” hardware vision platform combines “sensing”, “computing” and “storage” not only to overcome the von Neumann bottleneck of conventional complementary metal oxide semiconductor (CMOS) technology but also to eliminate the need for peripheral circuits and sensors.


2021 ◽  
Author(s):  
Pin Tian ◽  
Hongbo Wu ◽  
Libin Tang ◽  
Jinzhong Xiang ◽  
Rongbin Ji ◽  
...  

Abstract Two-dimensional (2D) materials exhibit many unique optical and electronic properties that are highly desirable for application in optoelectronics. Here, we report the study of photodetector based on 2D Bi2O2Te grown on n-Si substrate. The 2D Bi2O2Te material was transformed from sputtered Bi2Te3 ultrathin film after rapid annealing at 400 ℃ for 10 min in air atmosphere. The photodetector was capable of detecting a broad wavelength from 210 nm to 2.4 μm with excellent responsivity of up to 3x105 and 2x104 AW-1, and detectivity of 4x1015 and 2x1014 Jones at deep ultraviolet (UV) and short-wave infrared (SWIR) under weak light illumination, respectively. The effectiveness of 2D materials in weak light detection was investigated by analysis of the photocurrent density contribution. Importantly, the facile growth process with low annealing temperature would allow direct large-scale integration of the 2D Bi2O2Te materials with complementary metal-oxide–semiconductor (CMOS) technology.


Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.


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