The Effect of Amorphous Silicon Layer in PE-CVD Titanium Polycide Gate Dielectrics

1990 ◽  
Vol 182 ◽  
Author(s):  
Shih-Chang Chen ◽  
Akihiro Sakamoto ◽  
Hiroyuki Tamura ◽  
Masaki Yoshimaru ◽  
Masayoshi Ino
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Film Surface ◽  
Silicon Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Native Oxide ◽  
Chemical Vapor Deposition Method ◽  
Dielectric Degradation

AbstractTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a—Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE—CVD). The effect of a—Si layer in PE—CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a—Si layer effect, three types of samples were prepared on gate SiO2 film with following structures: a) a—Si / TiSil.1 / a—Si / phosphorus (P) doped poly—Si, b) a—Si / TiSi1.1 / non—doped poly—Si / P doped poly—Si and c) a—Si / TiSi1.1 / P doped poly—Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre—cleaning treatment was performed in—situ on the poly—Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE—CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a—Si film as the under layer in decreasing the gate dielectric degradation. This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly—Si films, whichrestrains the TiSix local penetration.

The Effect of Amorphous Silicon Layer in Pe-Cvd Titanium Polycide Gate Dielectrics

1990 ◽  
Vol 181 ◽  
Author(s):  
Shih-Chang Chen ◽  
Akihiro Sakamoto ◽  
Hiroyuki Tamura ◽  
Masaki Yoshimaru ◽  
Masayoshi Ino
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Film Surface ◽  
Silicon Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Native Oxide ◽  
Chemical Vapor Deposition Method ◽  
Dielectric Degradation

ABSTRACTTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a-Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE-CVD). The effect of a-Si layer in PE-CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a-Si layer effect, three types of samples were prepared on gate SiO2 film with following structures : a) a-Si / TiSi-1.1 / a-Si / phosphorus (P) doped poly-Si, b) a-Si / TiSi-1.1 / non-doped poly-Si / P doped poly-Si and c) a-Si / TiSi1.1 / P doped poly-Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre-cleaning treatment was performed in-situ on the poly-Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE-CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a-Si film as the under layer in decreasing the gate dielectric degradation . This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly-Si films, which restrains the TiSix local penetration.

Limiting Native Oxide Regrowth for High-k Gate Dielectrics

2003 ◽  
Vol 765 ◽  
Author(s):  
K. Choi ◽  
H. Harris ◽  
S. Gangopadhyay ◽  
H. Temkin
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Hafnium Dioxide ◽  
Electron Beam Evaporation ◽  
Native Oxide ◽  
Device Applications ◽  
The Difference ◽  
Cleaning Methods

AbstractA cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.

JVD Silicon Nitride and Titanium Oxide as Advanced Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
T.P. Ma
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Titanium Oxide ◽  
Vapor Deposition ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Jet Vapor Deposition ◽  
Mos Gate

ABSTRACTThe principle and practice of the Jet-Vapor Deposition (JVD) technique for thin-film deposition will be introduced, followed by a presentation of the properties of ultra-thin JVD silicon nitride (designated SiN in this paper) as advanced MOS gate dielectric. Recent results on the JVD TiO2/SiN gate stack will also be presented

BCl3/N2 Plasma for Advanced non-Si Gate Patterning

2006 ◽  
Vol 913 ◽  
Author(s):  
Denis Shamiryan ◽  
Vasile Paraschiv ◽  
Salvador Eslava-Fernandez ◽  
Marc Demand ◽  
Mikhail Baklanov ◽  
...  
Keyword(s):  
Deposition Rate ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Film Surface ◽  
Ion Bombardment ◽  
Film Deposition ◽  
High Deposition Rate ◽  
Lateral Direction ◽  
Metal Gates ◽  
Profile Control

AbstractAs conventional materials in CMOS manufacturing, Si as a gate material and SiO2 as a gate dielectric, approach their performance limit, the search for new materials becomes key point. Patterning of the new stacks containing these materials require both new plasma etch chemistries and new approaches.We propose a BCl3/N2 based plasma mixture for the advanced gate patterning (in this case pure Ge gates and TaN metal gates). There are three reasons to select this combination:a) The gas mixture generates Cl* species able to etch a diversity of materials, b) it is selective towards Si due to formation of passivating Si-B bonds and c) it improves profile control possibly by formation of a passivating BN-like film on feature side walls. It was found that BCl3 in presence of N2 results in a film deposition if no bias is applied to the substrate (i.e. there is no ion bombardment). The film is hexagonal BN-like since the characteristic peaks corresponding to the in-plane B-N and out-of-plane B-N-B bonds were found in FTIR spectra. The composition of the film surface as found by XPS is B, N and O (as no O2 is present in the plasma it may be a result of oxidation in the atmosphere), the amount of Cl is approx. 1%. The film is soluble in water that makes its removal easy. The deposition rate can be as high as 300 nm/min depending on plasma power, pressure, flow rates and BCl3 to N2 ratio.We propose to use the BCl3/N2 mixture to etch materials too sensitive to Cl-based plasma. Pure BCl3 plasma might distort gate profiles, as materials are etched in a lateral direction as well, this is the case, e.g. for pure Ge gates. Addition of small amount of nitrogen (5% to 10%) to the BCl3 plasma preserves the vertical profile, apparently by the formation of a passivating BN-like layer on the vertical surfaces where there is no ion bombardment. Too high nitrogen concentration results in positively sloped gate profile or even in the etch stop that could be attributed to the too high deposition rate that exceeds the etch rate. All experiments have been performed in Lam Versys 2300 etch chamber.

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

2009 ◽  
Vol 105 (12) ◽  
pp. 124504 ◽  
Author(s):  
S. L. Rumyantsev ◽  
Sung Hun Jin ◽  
M. S. Shur ◽  
Mun-Soo Park
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Low Frequency ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Silicon Thin Film

Determination of Thermal Conductivity of Amorphous Silicon Thin Films via Non-Contacting Optical Probing

2006 ◽  
Vol 326-328 ◽  
pp. 689-692
Author(s):  
Seung Jae Moon
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thermal Conductivity ◽  
Amorphous Silicon ◽  
Optical Transmission ◽  
Film Deposition ◽  
Transmission Measurement ◽  
Conductive Heat ◽  
Optical Transmission Measurement

The thermal conductivity of amorphous silicon (a-Si) thin films is determined by using the non-intrusive, in-situ optical transmission measurement. The thermal conductivity of a-Si is a key parameter in understanding the mechanism of the recrystallization of polysilicon (p-Si) during the laser annealing process to fabricate the thin film transistors with uniform characteristics which are used as switches in the active matrix liquid crystal displays. Since it is well known that the physical properties are dependent on the process parameters of the thin film deposition process, the thermal conductivity should be measured. The temperature dependence of the film complex refractive index is determined by spectroscopic ellipsometry. A nanosecond KrF excimer laser at the wavelength of 248 nm is used to raise the temperature of the thin films without melting of the thin film. In-situ transmission signal is obtained during the heating process. The acquired transmission signal is fitted with predictions obtained by coupling conductive heat transfer with multi-layer thin film optics in the optical transmission measurement.

Amorphous Phase Formation of Titanium Silicide on The 4° off-Axis and on-Axis Si(100) Substrates

1996 ◽  
Vol 427 ◽  
Author(s):  
Hyeongtag Jeon ◽  
Sukjae Lee ◽  
Hwackjoo Lee ◽  
Hyun Ruh
Keyword(s):  
Layer Thickness ◽  
Amorphous Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Atomic Scale ◽  
Phase Identification ◽  
Atomic Steps ◽  
Si Substrates ◽  
Annealing Temperatures ◽  
Scale Roughness

AbstractTwo different Si(100) substrates, the 4°off-axis and the on-axis Si(100), were prepared. Ti thin films were deposited in an e-beam evaporation system and the amorphous layers of Ti-silicide were formed at different annealing temperatures. The Si(100) substrates before Ti film deposition were examined with AFM to verify the atomic scale roughness of the initial Si substrates. The amorphous layer was observed by HRTEM and TEM. And the chemical analysis and phase identification were examined by AES and XRD. The Si(100) substrate after HF clean shows the atomic scale microroughness such as atomic steps and pits on the Si surface. The on-axis Si(100) substrate exhibits much rougher surface morphologies than those of the off-axis Si(100). These differences of atomic scale roughnesses of Si substrates result in the difference of the thicknesses of amorphous Ti-silicide layers. The amorphous layer thicknesses on the on-axis exhibit thicker than those of the off-axis Si(100) and these differences inamorphous layer thicknesses became decreased as annealing temperatures increased. These indicate that the role of the atomic scale roughness on the amorphous layer thickness is much significant at low temperatures. In this study, the correlation between the atomic scale roughness and the amorphous layer thickness is discussed in terms of the atomic steps and pits based on the observation with using analysis tools such as AFM, TEM and HRTEM.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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