Ultrathin Soi Structures by Low Energy Oxygen Implantation

1991 ◽  
Vol 235 ◽  
Author(s):  
Fereydoon Namavar ◽  
E. Cortesi ◽  
B. Buchanan ◽  
J. M. Manke ◽  
N. M. Kalkhoran
Keyword(s):  
Low Energy ◽  
Radiation Hardness ◽  
Silicon On Insulator ◽  
Great Promise ◽  
High Quality ◽  
Fully Depleted ◽  
Device Structures ◽  
Ultrathin Soi ◽  
Radiation Hard ◽  
Standard Energy

ABSTRACTAlthough silicon-on-insulator (SOI) materials made by standard energy (150–200 keV) SIMOX processes have shown great promise for meeting the needs of radiation hard microelectronics, there are still problems relating to the radiation hardness and economic viability of standard SIMOX. A low energy SIMOX (LES) process reduces cost and improves radiation hardness and increased throughput of any implanter because much smaller doses are required. In addition, the process is uniquely able to produce high quality thin SIMOX structures that are of particular interest for fully depleted device structures. In this paper, we address the formation of high quality ultrathin SIMOX structures by low energy implantation.

Ultrathin Low Energy Simox for Low Cost, High Density Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
Fereydoon Namavar ◽  
N.M. Kalkhoran ◽  
A. Cremins
Keyword(s):  
Low Cost ◽  
Electrical Characterization ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Great Promise ◽  
Fully Depleted ◽  
Device Structures ◽  
Radiation Hard ◽  
Standard Energy

ABSTRACTSilicon-on-insulator (SOI) materials made by standard energy (150 to 200 keV) separation by implantation of oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. Since much smaller doses are required, low energy SIMOX (LES) reduces cost, improves radiation hardness, and increases the throughput of any ion implanter. The process can also produce high quality thin SIMOX structures that are of particular interest for fully depleted and submicron device structures. In this paper, we address the formation as well as the material and electrical characterization of LES wafers and compare them with standard SIMOX wafers.

On the Formation of Ultrathin Simox Structures by Low Energy Implantation

1992 ◽  
Vol 284 ◽  
Author(s):  
F. Namavar ◽  
B. Buchanan ◽  
N. M. Kalkhoran
Keyword(s):  
Integrated Circuits ◽  
Substrate Material ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Great Promise ◽  
Ultrathin Layers ◽  
Commercial Applications ◽  
Competitive Substrate ◽  
The Cost ◽  
Radiation Hard

ABSTRACTSilicon-on-insulator (SOI) wafers made by standard energy (150–200 keV) Separation by IMplantation of Oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. However, if SIMOX material is to become a competitive substrate material for manufacturing commercial integrated circuits, the cost of the SIMOX wafers must be greatly reduced. The low energy SIMOX (LES) process accomplishes the needed reduction in cost by producing ultrathin layers which require much lower ion doses. These ultrathin layers are necessary for the next generation of commercial ultra high density CMOS integrated circuits, and must be of very high quality to be utilized for commercial applications. In this paper we discuss characterization of ultrathin LES structures.

scholarly journals The Effect of Energy Loss Straggling on SEUs Induced by Low-Energy Protons in 28 nm FDSOI SRAMs

2019 ◽  
Vol 9 (17) ◽  
pp. 3475
Author(s):  
Lujie Zhang ◽  
Jingyan Xu ◽  
Yaqing Chi ◽  
Yang Guo
Keyword(s):  
Energy Loss ◽  
Random Access ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Sensitive Volume ◽  
Access Memory ◽  
Fully Depleted ◽  
Direct Ionization ◽  
Single Event Upsets ◽  
28 Nm

Sensitive volume thickness for silicon on insulator (SOI) devices has scaled to the point that energy loss straggling cannot be ignored within the development of the manufacturing process. In this study, irradiation experiments and Geant4 simulation were carried out to explore the influence of energy loss straggling on single event upsets (SEUs) caused by sub-8 MeV proton direct ionization. We took a 28 nm fully-depleted SOI static random-access memory (SRAM) as the research target. According to our results, the depositing energy spectrum formed by monoenergetic low-energy protons that penetrated through the sensitive volume of the target SRAM was extremely broadened. We concluded that the SEUs we observed in this article were attributed to energy loss straggling. Therefore, it is sensible to take the new mechanism into consideration when predicting proton-induced SEUs for modern nanometer SOI circuits, instead of the traditional linear energy transfer (LET) method.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

2011 ◽  
Author(s):  
Liew Kaeng Nan ◽  
Lee Meng Lung
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Critical Dimension ◽  
Low Energy ◽  
Ex Situ ◽  
Good Image Quality ◽  
Ion Beam Etching ◽  
Device Structures ◽  
Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

Constructed reed beds: appropriate technology for small communities

1995 ◽  
Vol 32 (3) ◽  
pp. 339-348 ◽  
Author(s):  
M. B. Green ◽  
J. Upton
Keyword(s):  
Sewage Treatment ◽  
Appropriate Technology ◽  
Great Promise ◽  
High Quality ◽  
Reed Beds ◽  
Small Communities ◽  
Operational Information ◽  
Reed Bed ◽  
Small Sites ◽  
Very High

Reed bed treatment is put in the context of a major water company’s need to provide reliable, high quality, effluents from small sewage treatment works whilst seeking to minimise running costs. Design and operational information is given for reed bed applications in Severn Trent Water. Performance details are provided for application to secondary, tertiary and storm overflow treatment. The results give particular confidence in the system’s ability to deliver very high quality effluents when used for tertiary treatment, the company’s biggest application. Reed beds work well against less demanding criteria for secondary treatment at small sites and show great promise for storm overflow treatment.

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

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