Nanoporous Silica For Low K Dielectrics

1998 ◽  
Vol 511 ◽  
Author(s):  
T. Ramos ◽  
K. Rhoderick ◽  
R. Roth ◽  
L. Brungardt ◽  
S. Wallace ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Pore Size ◽  
Integrated Circuit ◽  
Dielectric Material ◽  
Scale Up ◽  
Nanoporous Silica ◽  
Interconnect Delay ◽  
Small Pore ◽  
Deposition Processes ◽  
Technology Nodes

ABSTRACTAs integrated circuit sizes decrease below 0.25 microns, device performance will no longer improve at the same rate as for past generations because of RC interconnect delay which becomes significant as compared to the intrinsic gate delay. Parallel approaches to address this are to use a lower resistance metal (i.e., copper instead of aluminum) and to use a dielectric material with a dielectric constant significantly below that of dense silica (∼4). Recently, considerable progress has been made in development of thin films of nanoporous silica for these applications. Advantages include high thermal stability, small pore size, similarity to conventional spin-on deposition processes and spin-on glass precursors and final material (silica). The dielectric constant of nanoporous silica can be tailored between ∼1 and 3 which allows its’ implementation at multiple technology nodes in integrated circuit manufacture.Recent development efforts have been focused on; 1) simpler and more reproducible deposition processes, 2) a more complete understanding of processing-property relationships for this material, 3) scale-up of manufacturing to yield a range of precursor products with stability for at least six months and very high purity, and 4) working with customers to integrate this material into both aluminum/gapfill and copper/damascene process flows. This paper targets several specific issues related to nanoporous silica use including water adsorption, pore size distribution control, processing at commercially viable throughputs, and obtaining thickness and dielectric uniformity across 200 mm wafers and wafer to wafer.

Nanoporous Silica for Low κ Dielectrics

1997 ◽  
Vol 495 ◽  
Author(s):  
Teresa Ramos ◽  
Steve Wallace ◽  
Douglas M. Smith
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuit ◽  
Dielectric Material ◽  
Fundamental Problem ◽  
Scale Up ◽  
Current Status ◽  
Nanoporous Silica ◽  
Interconnect Delay ◽  
Small Pore ◽  
Deposition Processes

ABSTRACTAs integrated circuit sizes decrease below 0.25 microns, device performance will no longer improve at the same rate as for past generations because of RC interconnect delay which becomes significant as compared to the intrinsic gate delay. The parallel approaches to partially address this fundamental problem are to use a lower resistance metal (i.e., copper instead of aluminum) and to use a dielectric material with a dielectric constant significantly below that of dense silica (∼4). Recently, considerable progress has been made in development of thin films of nanoporous silica (also known as aerogels or low density xerogels) for these ILD and IMD applications. Advantages of these materials include high thermal stability, small pore size, and similarity to conventional spin-on deposition processes, spin-on glass precursors and final material (silica). The dielectric constant of nanoporous silica can be tailored between ∼1 and 3 which allows its’ implementation at multiple technology nodes in integrated circuit manufacture starting with the 0.18 micron node.Research and development efforts at Nanoglass over the last several years have focused on; 1) simpler and more reproducible deposition processes, 2) a more complete understanding of processing-property relationships for this material, 3) scale-up of manufacturing to yield a range of precursor products with stability for at least six months and very high purity, and 4) working with customers to integrate this material into both aluminum/gapfill and copper/damascene process flows. Nanoglass has now developed a new process which considerably reduces the number of process steps and allows independent control of both film thickness and porosity. The current status of process and precursor development and device integration efforts for nanoporous silica is discussed.

Nanoporous Silica for Low k Dielectrics

1996 ◽  
Vol 443 ◽  
Author(s):  
Teresa Ramos ◽  
Kevin Roderick ◽  
Alok Maskara ◽  
Douglas M. Smith
Keyword(s):  
Thin Films ◽  
Dielectric Constant ◽  
Film Thickness ◽  
Pore Size ◽  
Ambient Pressure ◽  
Porous Solids ◽  
Nanoporous Silica ◽  
Low Density ◽  
Trade Offs ◽  
Small Pore

AbstractConsiderable progress has been made in development of thin films of nanoporous silica (also known as aerogels or low density xerogels) for ILD and IMD applications. Advantages of these materials include high thermal stability, small pore size, and similarity to conventional deposition processes, precursors and final material (silica). We have previously reported success in synthesizing low density, low dielectric constant (K<2) thin films using ambient pressure processing. However, processing of those films was complicated due to large number of process steps and difficulties in independently controlling both film thickness and film porosity.Nanoglass has now developed a new process which considerably reduces the number of process steps and allows independent control of both film thickness and porosity. The dielectric constant of the films can be tailored between 1.3 and 2.5. These films have improved mechanical properties due to controlled pore size and narrow pore size distribution and also because of higher density. The trade-offs between density, mechanical strength and dielectric constant for these types of porous solids will be elucidated. The known properties of the film and the process flow for deposition and post-deposition curing and the role of the relative rates of reaction, gelation, aging, and drying will be presented.

Characterization of MgZnO Thin Film for 1 GHz MMIC Applications

2013 ◽  
Vol 832 ◽  
pp. 310-315
Author(s):  
R. Ahmad ◽  
M.S. Shamsudin ◽  
M. Salina ◽  
S.M. Sanip ◽  
M. Rusop ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Dielectric Constant ◽  
Loss Tangent ◽  
Integrated Circuit ◽  
Annealing Temperature ◽  
Dielectric Material ◽  
Sol Gel ◽  
Size Reduction ◽  
High Frequencies

MgZnO thin films are proposed as a new dielectric material for 1 GHz monolithic microwave integrated circuit (MMIC) applications. The high permittivity of this material enables size reduction; furthermore this can be fabricated using a low cost processing method. In this work, MgZnO/Pt/Si thin films were synthesized using a sol-gel spin coating method. The samples were annealed at various temperatures with the effects on physical and electrical properties investigated at direct current (DC) and high frequencies. The physical properties of MgZnO thin film were analyzed using X-Ray diffraction, with the improvements shown in crystalline structure and grain size with increasing temperature up to 700 °C. DC resistivity of 77 Ωcm at higher annealing temperature obtained using a four point probe station. In order to prove the feasibility at high frequencies, a test structure consisting of a 50 Ω transmission line and capacitors with 50 × 50 μm electrode area were patterned on the films using electron beam lithography. The radio frequency (RF) properties were measured using aWiltron 37269Avector network analyzer andCascade Microtechon-wafer probes measured over a frequency range of 0.5 to 3 GHz. The dielectric constant, loss tangent and return loss, S11improve with the increment annealing temperature. The dielectric constant was found to be 18.8, with loss tangent of 0.02 at 1 GHz. These give a corresponding size reduction of ten times compared to conventional dielectrics, silicon nitride (Si3N4). These indicate that the material is suitable to be implemented as a new dielectric material for 1GHz MMIC applications.

scholarly journals The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Materials ◽  
2021 ◽  
Vol 14 (17) ◽  
pp. 4827
Author(s):  
Nianmin Hong ◽  
Yinong Zhang ◽  
Quan Sun ◽  
Wenjie Fan ◽  
Menglu Li ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Data Storage ◽  
Integrated Circuit ◽  
Porous Silica ◽  
Dielectric Materials ◽  
Interlayer Dielectric ◽  
Damascene Process ◽  
Key Issues ◽  
Deposition Processes ◽  
Low K

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

Development of porous SiLK™ Semiconductor Dielectric Resin for the 65 nm and 45 nm Nodes

2003 ◽  
Vol 766 ◽  
Author(s):  
R. J. Strittmatter ◽  
J. L. Hahnfeld ◽  
H. C. Silvis ◽  
T. M. Stokich ◽  
J. D. Perry ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Pore Size Distribution ◽  
Pore Size ◽  
Size Distribution ◽  
Scale Up ◽  
Process Window ◽  
Pore Morphology ◽  
Monitoring And Control ◽  
Interlayer Dielectric ◽  
The Impact

AbstractPorous SiLK resin is an ultra-low-k interlayer dielectric (ILD) material designed to meet the needs of the 65 nm technology node and beyond. In early 2002, the porous SiLK resin formulation was defined and scaled up, facilitating the tight monitoring and control of key properties, including pore size distribution, over several lots of material. The film processing kinetics are now well understood and a wide process window exists which ensures optimum pore morphology and pore size distribution. Thermal cycling of films demonstrates no effect on pore morphology or dielectric constant. The material has been designed to minimize the impact of CTE mismatch at high temperature, which challenged the integration of some previous generations of SiLK and porous SiLK dielectric resins. The discrete, closed-cell pore geometry is well characterized and enables the extendibility of process module development from SiLK resin technology to porous SiLK resin. Concurrent with the scale up efforts, advancements in minimizing both cure time and temperature simultaneously, as well as significant improvements in pore size and pore size distribution, have been achieved. The cure and porogen burn out time has been reduced by 50% or greater, and the temperature has been reduced to 370°C. The pore size has been reduced by ∼35%, and the pore size distribution has been narrowed by ∼40%. These advancements have resulted in the introduction of porous SiLK T resin, with a dielectric constant of k = 2.4 and a recommended cure temperature of 370°C, and the introduction of porous SiLK U resin, with a mean pore diameter of ∼5 nm and a dielectric constant of k = 2.2.

Porous Silica Xerogel Processing And Integration For Ulsi Applications

1998 ◽  
Vol 511 ◽  
Author(s):  
Changming Jin ◽  
Scott List ◽  
Eden Zielinski
Keyword(s):  
Dielectric Constant ◽  
Dielectric Material ◽  
Porous Silica ◽  
Thin Film Deposition ◽  
Deposition Process ◽  
Film Deposition ◽  
Silica Xerogel ◽  
Future Technology ◽  
Small Pore ◽  
High Dielectric

ABSTRACTWith a tunable ultra low dielectric constant, porous silica xerogel is an attractive dielectric material for ULSI interconnect applications and is potentially extendable to multiple future technology nodes. Porous silica xerogel films have been processed and integrated into device test structures as ultra low k intermetal dielectrics. A fully automated thin film deposition process is recently developed and gives high throughput and good repeatability. A surface modification technique is used to make the films hydrophobic. The film dielectric constant is measured to be less than 2, depending on porosity. Because of the small pore sizes, the films display high dielectric break down strength. With proper shrinkage control, porous silica xerogel shows excellent gapfill capabilities. Integration of the porous silica xerogel material into CMP planarized double level metal (DLM) test structures with both Al and W plugs in a gapfill scheme is successful. Porous silica xerogel structures provide 14% and 35% total capacitance reduction compared to structures with hydrogen silsesquioxane (HSQ) and high density plasma (HDP) oxide respectively. Reliability and current leakage data of porous silica xerogel are comparable to that of HSQ. Feasibility of integrating porous silica xerogel into Cu damascene structures is also demonstrated. Cu/xerogel damascene structures exhibit improvements in both resistance and capacitance compared with convention Al/Oxide gapfill structures.

Characterization and Integration in Cu Damascene Structures of AURORA, an Inorganic Low-k Dielectric

2000 ◽  
Vol 612 ◽  
Author(s):  
R. A. Donaton ◽  
B. Coenegrachts ◽  
E. Sleeckx ◽  
M. Schaekers ◽  
G. Sophie ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Pore Size ◽  
Carbon Concentration ◽  
Low Carbon ◽  
Small Pore Size ◽  
Damascene Process ◽  
Small Pore ◽  
Line Spacing ◽  
Low K

AbstractAURORA films, which have a Si-O-Si network with –CH3 terminations, were characterized and integrated into Cu single damascene structures. The relatively low carbon concentration (∼ 20%) and the very small pore size (∼ 0.6 nm) found could be advantageous during integration of AURORA. Integration of AURORA into Cu single damascene structures was successfully achieved. Suitable resist strip processes, which are critical for Si-O-C type materials, were developed, resulting in trenches with satisfactory profiles. After a complete single damascene process, a interline dielectric constant value of 2.7 was found for line spacing down to 0.25 µm.

Impact of Pore Size and Morphology of Porous Organosilicate Glasses on Integrated Circuit Manufacturing

2006 ◽  
Vol 914 ◽  
Author(s):  
Mark O'Neill ◽  
Mary K Haas ◽  
Brian K Peterson ◽  
Raymond N Vrtis ◽  
Scott J Weigel ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Dielectric Constant ◽  
Pore Size ◽  
Integrated Circuit ◽  
Network Connectivity ◽  
Chemical Vapor ◽  
Total Porosity ◽  
Molecular Volume ◽  
Porous Films ◽  
Organosilicate Glass

AbstractPorous organosilicate materials produced by plasma enhanced chemical vapor deposition are the leading candidates for back-end-of-line dielectric insulators for IC manufacturing at 45nm design features and beyond. The properties of porous organosilicate glass films of dielectric constant k=2.50 ± 0.05 formed using diethoxymethylsilane and five different porogen precursors with an ultraviolet post treatment are reported. By varying the porogen precursor type pore sizes of 1-2 nm (equivalent spherical diameter) and porosities in the range of 24-31% were measured. While there were no observable trends in pore size with the molecular volume or plasma reactivity of the porogen precursor, modulus values ranged from 6.6 to 10.8 GPa. Porous films with the highest mechanical properties were found to have the highest matrix dielectric constant, highest network connectivity (lowest methyl content), and highest density. Within this process space, maximizing the network connectivity of the film was found to be more important to mechanical properties than lowering the total porosity. In effect, the choice of porogen precursor dictates the film morphology through its impact on the organosilicate glass matrix and pore size.

The Effects of Oxygen Content on Bonding Configurations and Properties of Low-k Organosilicate Glass Dielectric Films

2008 ◽  
Vol 8 (5) ◽  
pp. 2549-2553
Author(s):  
Sheng-Wen Chen ◽  
Chuan-Pu Liu ◽  
Shiu-Ko Jangjian ◽  
Ying-Lang Wang
Keyword(s):  
Dielectric Constant ◽  
Pore Size ◽  
Chemical Vapor ◽  
Dielectric Films ◽  
Chemical Vapor Deposition Method ◽  
Cage Structure ◽  
Low Dielectric ◽  
Small Pore ◽  
Organosilicate Glass ◽  
Precursor Ratio

The low dielectric constant SiOC:H films of plasma enhanced chemical vapor deposition method have been developed with various precursor ratio. The reduction of the dielectric constant has been achieved by increasing the porosity in the films through the change of precursor ratio. In order to clarify the relation between dielectric constant and film porosity, the small angle X-ray scattering technique has been applied for characterizing pore size in the porous low-k dielectric films. The effects of the oxygen on the bonding configuration and electrical properties were investigated by adjusting TMS/O2 gas ratios. The porous SiOC:H film displays the small pore sizes and lower dielectric constant. It is found that the pore size of SiOC:H film is significant smaller than 1 nm and the pore size attributed to Si–O–Si cage structure change.

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