Self-Aligned Gate Metallization Processes with Low-Thermal Budget

ABSTRACTA novel concept for CMOS transistor gate metallization is described. It is featured with Gate Cloisonné, a process consisting of dielectric deposition over frontend transistors, followed by chemical mechanical polishing to re-expose the gate pattern on a planar dielectric background. Based on this concept, two metallization schemes have been developed. One is self-aligned metal gate process, which allows for low thermal budget gate metallization with element metals such as W and Al, resulting in a very low sheet resistance (< 1 Ω/sq). The other scheme is dual self-aligned silicidation, which enables decoupling of gate silicidation from that of source/drain silicon areas. Titanium based silicidation process is implemented to form thick silicide on narrow polysilicon gates and thin one over active silicon areas. Low gate sheet resistance (≈ 1.9Ω/sq) is achieved with complete suppression of linewidth effects. Both the metallization schemes are a priori scaleable to deep submicron technologies and suitable to fabricating ultra-shallow junction devices with very low gate sheet resistance. Both of them have been implemented in a 0.25-μm CMOS technology.

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Integration of NiSi SALICIDE for Deep Submicron CMOS Technologies

MRS Proceedings ◽

10.1557/proc-514-179 ◽

1998 ◽

Vol 514 ◽

Cited By ~ 8

Author(s):

X. W. Lin ◽

N. Ibrahim ◽

L. Topete ◽

D. Pramanik

Keyword(s):

Thin Films ◽

Single Crystal ◽

Sheet Resistance ◽

Thermal Annealing ◽

Cmos Technology ◽

Deep Submicron ◽

Thermal Budget ◽

Si Substrates ◽

Low Thermal Budget ◽

Lower Resistivity

ABSTRACTA NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

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Reduction of Sheet Resistance and Low-Thermal-Budget Relaxation of Stress Gradients in Polysilicon Microcantilever Beams Using Nickel-Silicides

Journal of Microelectromechanical Systems ◽

10.1109/jmems.2007.892898 ◽

2007 ◽

Vol 16 (2) ◽

pp. 279-288 ◽

Cited By ~ 11

Author(s):

Tae June Kang ◽

Ho-Young Lee ◽

Yong Hyup Kim

Keyword(s):

Sheet Resistance ◽

Thermal Budget ◽

Stress Gradients ◽

Nickel Silicides ◽

Low Thermal Budget

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NEW ROBUST n+/p+ DUAL-GATE CMOS TECHNOLOGY OPTIMIZED FOR LOW POWER OPERATION

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156494000073 ◽

1994 ◽

Vol 05 (02) ◽

pp. 135-143 ◽

Cited By ~ 1

Author(s):

D.C.H. YU ◽

K.H. LEE ◽

A. KORNBLIT ◽

C.C. FU ◽

R.H. YAN ◽

...

Keyword(s):

Low Power ◽

Sheet Resistance ◽

Cmos Technology ◽

Design Rule ◽

Gate Stack ◽

Thermal Budget ◽

Critical Issues ◽

Dual Gate ◽

Power Operation ◽

Symmetric Surface

A novel optimized dual-gate technology ( p +-gate for PMOS and n +-gate for NMOS) for symmetric surface-channel CMOS devices is developed to fabricate low-power components. This technology features a WSi x-polycide gate dopant drive-out technique to dope the n + and p + gate and a TiN shunt process to connect the dual-gate. We demonstrate that the critical issues associated with a dual-gate technology are resolved by this new and robust technology. There are no design rule penalties for gate layout width or n + to p + source/drain separation with this process. The CMOS devices are scalable even down to 0.1 μm gates due to the design rule advantages. No degradation is measured in device characteristics due to the diffusion of gate dopants either laterally between an opposite type of gate or vertically through the gate stack. Ion penetration during gate implant is also effectively suppressed by the new gate stack. No degradation in gate sheet resistance, R s, is detected. The most severe annealing condition tested in this work is 900°C for 30 minutes. Therefore, plenty of thermal budget is allowed is this technology. This improvement not only adds to the robustness of the technology but also increases the conductance of the gate runner.

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Study of Nitrogen Incorporation in Gate Oxides Using the Resistance to Oxidation Method

MRS Proceedings ◽

10.1557/proc-429-251 ◽

1996 ◽

Vol 429 ◽

Cited By ~ 4

Author(s):

I. Sagnes ◽

D. Laviale ◽

M. Regache ◽

F. Glowacki ◽

L. Deutschmann ◽

...

Keyword(s):

Nitrogen Concentration ◽

Gate Oxide ◽

Cmos Technology ◽

Gate Oxides ◽

Thermal Budget ◽

Nitrogen Incorporation ◽

Resistance To Oxidation ◽

Low Thermal Budget ◽

Direct Use ◽

Low Nitrogen

Numerous nitridation processes have been studied to obtain very thin (≤ 6 nm), reproducible and reliable gate oxides. Recent results (1,2,3) have confirmed that i) the NO molecule is the species responsible for the nitrogen incorporation at the SiO2/Si interface and that ii) the direct use of NO gas allows the gate oxide to be nitrided at low thermal budget whilst maintaining the same advantages as those of N2O nitridation. NO nitridation of very thin oxides has so far been inadequately documented in terms of incorporated nitrogen concentration at the SiO2/Si interface. It is of prime importance to control the incorporation of a few nitrogen monolayers at the SiO2/Si interface, particularly for device performances in the 0. 18μm CMOS technology. In the following we present results on the control of low nitrogen concentration in pure NO atmosphere, with particular emphasis on a method based on the re-oxidation of nitrided oxides. This method can be used in a production line thus avoiding the high costs and long characterization times associated with SIMS measurements.

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Silicides for 65 nm CMOS and Beyond

MRS Proceedings ◽

10.1557/proc-765-d7.5 ◽

2003 ◽

Vol 765 ◽

Cited By ~ 16

Author(s):

Jorge A. Kittl ◽

Anne Lauwers ◽

Oxana Chamirian ◽

Mark Van Dal ◽

Amal Akheyar ◽

...

Keyword(s):

Thermal Stability ◽

Sheet Resistance ◽

Kinetic Studies ◽

Process Window ◽

Thermal Budget ◽

Diffusion Limited ◽

Mechanism Of Degradation ◽

Low Thermal Budget ◽

Thermal Stability Of ◽

Ni Silicides

AbstractAn overview of silicide development for the 65 nm node and beyond is presented. The scaling behavior of Co based and Ni based silicides to sub-100 nm junctions and sub-40 nm gate lengths was investigated. Co and Co-Ni silicides required a high thermal budget to achieve low diode leakage. Even for lower thermal budgets, the sheet resistance of Co and Co-Ni silicides increased at gate lengths below 40 nm. NiSi had low sheet resistance down to 30 nm gate lengths exhibiting a reverse linewidth effect (sheet resistance decreased with decreasing linewidth), achieved lower contact resistivity than CoSi2 and lower diode leakage for similar sheet resistance values. Bridging issues cannot be ignored for NiSi, in particular for thicker Ni films, higher RTP temperatures and in the presence of Ti. Material issues for the application of NiSi were also investigated. Ni2Si was found to grow with diffusion limited kinetics in the 225-300°C range, with an activation energy of 1.5 eV. Results of the kinetic studies were used to design a two-step RTP process that limited the silicide thickness on small features by a low thermal budget first RTP step, reducing the reverse linewidth effect and avoiding excessive silicidation. In the presence of an interfacial oxide, undesired epitaxial NiSi2 pyramidal grains grew directly at temperatures as low as 310°C on p+ Si. Thermal stability of NiSi was also investigated. We found that the initial mechanism of degradation for thin NiSi films was agglomeration, with activation energies of 2.5-3 eV. The surface after agglomeration remained quite flat with alternating NiSi and exposed Si areas, while the interface roughened significantly. Thick films also degraded initially by agglomeration at low temperatures, but by transformation to NiSi2 at higher temperatures. The addition of Pt improved thermal stability of NiSi films against agglomeration. The Ni/Si-Ge reaction was also studied, finding that the addition of Ge reduced the thermal process window and resulted in a slightly higher resistivity.

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Low-Resistivity Amorphous Silicon for Contacts Using Low-Temperature Rapid Thermal Annealing

MRS Proceedings ◽

10.1557/proc-258-99 ◽

1992 ◽

Vol 258 ◽

Author(s):

Lynnita Knoch ◽

Gordon Tam ◽

N. David Theodore ◽

Ron Pennell

Keyword(s):

Low Temperature ◽

Ion Implantation ◽

Grain Boundaries ◽

Amorphous Silicon ◽

Sheet Resistance ◽

Rapid Thermal Annealing ◽

Thermal Budget ◽

Temperature Rapid Thermal Annealing ◽

Low Thermal Budget ◽

Polycrystalline Deposition

ABSTRACTFabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.

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