Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

2000 ◽  
Vol 640 ◽  
Author(s):  
Nabil Sghaier ◽  
Abdel K. Souifi ◽  
Jean-Marie Bluet ◽  
Manuel Berenguer ◽  
Gérard Guillot ◽  
...  

ABSTRACTThe aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

1988 ◽  
Vol 116 ◽  
Author(s):  
T. Eshita ◽  
T. Suzuki ◽  
T. Hara ◽  
F. Mieno ◽  
Y. Furumura ◽  
...  

AbstractWe developed a heteroepitaxial growth technique for large-area β-SiC films on Si substrates without buffer layers at 850ºC and 1000ºC. The substrates were vicinal 4-inch (111) Si wafers. The β-SiC films had smooth surfaces and were crack-free. X-ray diffraction and electron diffraction analysis revealed that the films grown at 1000ºC were single crystals. Satisfactory characteristics were obtained in aMOSFET with a β-SiC/Si02/poly-Si substrate structure. Our evaluations indicate that the β-SiC films were high-quality crystals.


Materials ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 380
Author(s):  
Jun-Hyun Kim ◽  
Sanghyun You ◽  
Chang-Koo Kim

Si surfaces were texturized with periodically arrayed oblique nanopillars using slanted plasma etching, and their optical reflectance was measured. The weighted mean reflectance (Rw) of the nanopillar-arrayed Si substrate decreased monotonically with increasing angles of the nanopillars. This may have resulted from the increase in the aspect ratio of the trenches between the nanopillars at oblique angles due to the shadowing effect. When the aspect ratios of the trenches between the nanopillars at 0° (vertical) and 40° (oblique) were equal, the Rw of the Si substrates arrayed with nanopillars at 40° was lower than that at 0°. This study suggests that surface texturing of Si with oblique nanopillars reduces light reflection compared to using a conventional array of vertical nanopillars.


2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Yijie Li ◽  
Nguyen Van Toan ◽  
Zhuqing Wang ◽  
Khairul Fadzli Bin Samat ◽  
Takahito Ono

AbstractPorous silicon (Si) is a low thermal conductivity material, which has high potential for thermoelectric devices. However, low output performance of porous Si hinders the development of thermoelectric performance due to low electrical conductivity. The large contact resistance from nonlinear contact between porous Si and metal is one reason for the reduction of electrical conductivity. In this paper, p- and n-type porous Si were formed on Si substrate by metal-assisted chemical etching. To decrease contact resistance, p- and n-type spin on dopants are employed to dope an impurity element into p- and n-type porous Si surface, respectively. Compared to the Si substrate with undoped porous samples, ohmic contact can be obtained, and the electrical conductivity of doped p- and n-type porous Si can be improved to 1160 and 1390 S/m, respectively. Compared with the Si substrate, the special contact resistances for the doped p- and n-type porous Si layer decreases to 1.35 and 1.16 mΩ/cm2, respectively, by increasing the carrier concentration. However, the increase of the carrier concentration induces the decline of the Seebeck coefficient for p- and n-type Si substrates with doped porous Si samples to 491 and 480 μV/K, respectively. Power factor is related to the Seebeck coefficient and electrical conductivity of thermoelectric material, which is one vital factor that evaluates its output performance. Therefore, even though the Seebeck coefficient values of Si substrates with doped porous Si samples decrease, the doped porous Si layer can improve the power factor compared to undoped samples due to the enhancement of electrical conductivity, which facilitates its development for thermoelectric application.


2008 ◽  
Vol 600-603 ◽  
pp. 251-254 ◽  
Author(s):  
Yong Mei Zhao ◽  
Guo Sheng Sun ◽  
Xing Fang Liu ◽  
Jia Ye Li ◽  
Wan Shun Zhao ◽  
...  

Using AlN as a buffer layer, 3C-SiC film has been grown on Si substrate by low pressure chemical vapor deposition (LPCVD). Firstly growth of AlN thin films on Si substrates under varied V/III ratios at 1100oC was investigated and the (002) preferred orientational growth with good crystallinity was obtained at the V/III ratio of 10000. Annealing at 1300oC indicated the surface morphology and crystallinity stability of AlN film. Secondly the 3C-SiC film was grown on Si substrate with AlN buffer layer. Compared to that without AlN buffer layer, the crystal quality of the 3C-SiC film was improved on the AlN/Si substrate, characterized by X-ray diffraction (XRD) and Raman measurements.


2014 ◽  
Vol 881-883 ◽  
pp. 1117-1121 ◽  
Author(s):  
Xiang Min Zhao

ZnO thin films with different thickness (the sputtering time of AlN buffer layers was 0 min, 30 min,60 min, and 90 min, respectively) were prepared on Si substrates using radio frequency (RF) magnetron sputtering system.X-ray diffraction (XRD), atomic force microscope (AFM), Hall measurements setup (Hall) were used to analyze the structure, morphology and electrical properties of ZnO films.The results show that growth are still preferred (002) orientation of ZnO thin films with different sputtering time of AlN buffer layer,and for the better growth of ZnO films, the optimal sputtering time is 60 min.


1987 ◽  
Vol 91 ◽  
Author(s):  
N. El-Masry ◽  
N. Hamaguchi ◽  
J.C.L. Tarn ◽  
N. Karam ◽  
T.P. Humphreys ◽  
...  

ABSTRACTInxGa11-xAs-GaAsl-yPy strained layer superlattice buffer layers have been used to reduce threading dislocations in GaAs grown on Si substrates. However, for an initially high density of dislocations, the strained layer superlattice is not an effective filtering system. Consequently, the emergence of dislocations from the SLS propagate upwards into the GaAs epilayer. However, by employing thermal annealing or rapid thermal annealing, the number of dislocation impinging on the SLS can be significantly reduced. Indeed, this treatment greatly enhances the efficiency and usefulness of the SLS in reducing the number of threading dislocations.


2012 ◽  
Vol 2012 ◽  
pp. 1-6
Author(s):  
Im Taek Yoon ◽  
Yoon Shon ◽  
Younghae Kwon ◽  
Young S. Park ◽  
Chang Soo Park ◽  
...  

We have investigated the magnetic and optical properties of dislocation-free vertical GaN nanorods with diameters of 150 nm grown on (111) Si substrates by radio-frequency plasma-assisted molecular-beam epitaxy followed by Mn ion implantation and annealing. The GaN nanorods are fully relaxed and have a very good crystal quality characterized by extremely strong and narrow photoluminescence excitonic lines near 3.47 eV. For GaMnN nanorods, it can be concluded that the ferromagnetic property of GaMnN nanorod with a Curie temperature over 300 K is associated with the formation of Mn4Si7magnetic phase which results from the effects of magnetic and structural disorder introduced by a random incorporation and inhomogeneous distribution of Mn atoms in the porous layer between the nanorods that form precipitates in the Si substrate before or during the annealing step amongst the GaN nanorods.


2003 ◽  
Vol 93 (1) ◽  
pp. 362-367 ◽  
Author(s):  
Michael E. Groenert ◽  
Christopher W. Leitz ◽  
Arthur J. Pitera ◽  
Vicky Yang ◽  
Harry Lee ◽  
...  

1995 ◽  
Vol 379 ◽  
Author(s):  
Jeffrey J. Welser

ABSTRACTThe experimental application of strained-Si / relaxed-Si1−xGex heterostructures to n-MOSFETs is discussed, focusing on the enhanced mobility provided by the strain. This paper provides an overview of the theoretically-predicted electronic properties of these heterostructures, as well as their growth. Several practical issues which arise in MOS applications are covered, including the effect of the relaxed-Si1−xGex, buffer layers on diode performance, and the observation of self-heating effects in the output characteristics of the MOS transistors.


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