scholarly journals A reliability study of Non-uniform Si TFET with dual material source: Impact of interface trap charges and temperature

2021 ◽  
Author(s):  
Jagritee Talukdar ◽  
Kavicharan Mummaneni
Keyword(s):  
Interface Trap ◽  
Small Signal ◽  
Reliability Study ◽  
Material Source ◽  
Dc Characteristics ◽  
Signal Parameters ◽  
Source Voltage ◽  
The Impact ◽  
Dual Material ◽  
Trap Charges

Abstract The article reports the extraction of DC characteristics and small signal parameters of Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. The reliability of the device is examined by analysing: 1) the impact of the presence of interface trap charges, 2) the impact of temperature variation (200 K- 400 K). In the analysis it has been observed that in case of absence of interface trap charges the increase in frequency reduces the value of parasitic capacitances. In addition, the presence of interface trap charges lessens the value of parasitic capacitances up to a certain gate to source voltage after that it shows a reverse effect. Further, it has been perceived that the effect of change in temperature is more on device ambipolar current when interface trap charges are present, whereas the reverse is true in the case of OFF state current and different parasitic capacitances.

SMALL SIGNAL AND DC CHARACTERISTICS OF ULTRA-THIN GaN/AlN/GaN HFETs

2011 ◽  
Vol 20 (03) ◽  
pp. 385-392 ◽  
Author(s):  
KELSON D. CHABAK ◽  
DENNIS E. WALKER ◽  
ANTONIO CRESPO ◽  
MANUEL TREJO ◽  
MAURICIO KOSSLER ◽  
...  
Keyword(s):  
Sapphire Substrate ◽  
High Performance ◽  
Gate Dielectric ◽  
Small Signal ◽  
Barrier Thickness ◽  
Gate Leakage ◽  
Performance Factors ◽  
Dc Characteristics ◽  
Signal Parameters

This paper presents high performance device results using an ultra-thin AlN / GaN structure on sapphire substrate with a 100-nm T -gate. Excellent dc and RF characteristics are reported, including an extrinsic transconductance of 500 mS/mm and an extrinsic f t / f max ( U ) ratio of 78/111-GHz which is among the highest reported for AlN / GaN HFETs. Low gate leakage results are also presented despite the small barrier thickness and absence of a gate dielectric. Modeling of the small signal parameters is also discussed to gain an understanding of the limiting and contributing performance factors.

scholarly journals Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

2021 ◽  
Author(s):  
Rinku Rani Das ◽  
Atanu Chowdhury ◽  
Apurba Chakroborty ◽  
Santanu Maity
Keyword(s):  
Semiconductor Device ◽  
Cmos Technology ◽  
The Other ◽  
Interface Trap ◽  
Trap Concentration ◽  
Device Efficiency ◽  
The Impact ◽  
First Time ◽  
Intrinsic Gain ◽  
Trap Charges

Abstract Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.

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