High blocking voltage ESD timer clamp with mis-trigger protection

Author(s):  
Sirui Luo ◽  
Srivatsan Parthasarathy ◽  
Javier A. Salcedo ◽  
Jean-Jacques Hajjar
Keyword(s):  
Author(s):  
Aleksey Bogachev ◽  
Vladimir Krylov

The results of an experiment to determine the activation energy of a deep level in a gallium arsenide mesastructure by capacitive relaxation spectroscopy of deep levels at various values of the blocking voltage are considered.


2020 ◽  
Vol 67 (12) ◽  
pp. 5628-5632
Author(s):  
Zhuangzhuang Hu ◽  
Jianguo Li ◽  
Chunyong Zhao ◽  
Zhaoqing Feng ◽  
Xusheng Tian ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.


1993 ◽  
Vol 296 (2) ◽  
pp. 309-312 ◽  
Author(s):  
M F Rossier ◽  
C P Python ◽  
M M Burnay ◽  
W Schlegel ◽  
M B Vallotton ◽  
...  

Thapsigargin, an inhibitor of the microsomal Ca2+ pumps, has been extensively used to study the intracellular Ca2+ pool participating in the generation of the agonist-induced Ca2+ signal in various cell types. A dual effect of this agent was observed in bovine adrenal zona glomerulosa cells. At nanomolar concentrations, thapsigargin stimulated a sustained Ca2+ influx, probably resulting from Ca(2+)-store depletion. In contrast, when added at micromolar concentrations, thapsigargin prevented the rise in cytosolic free Ca2+ concentration ([Ca2+]c) induced by K+. This inhibitory effect of thapsigargin on voltage-activated Ca2+ channels was confirmed by measuring Ba2+ currents by the patch-clamp technique. Both low-threshold (T-type) and high-threshold (L-type) Ca2+ channels were affected by micromolar concentrations of thapsigargin. Analysis of the current-voltage relationship for T-type channels revealed that thapsigargin did not modify the sensitivity of these channels to the voltage, but decreased the maximal current flowing through the channels. In conclusion, thapsigargin appears to exert a dual effect on adrenal glomerulosa cells. At lower concentrations, this agent induces a sustained Ca2+ entry, whereas at higher concentrations it decreases [Ca2+]c by blocking voltage-activated Ca2+ channels.


2008 ◽  
Vol 600-603 ◽  
pp. 1187-1190 ◽  
Author(s):  
Q. Jon Zhang ◽  
Charlotte Jonas ◽  
Joseph J. Sumakeris ◽  
Anant K. Agarwal ◽  
John W. Palmour

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
M. Jagabar Sathik ◽  
Dhafer J. Almakhles ◽  
N. Sandeep ◽  
Marif Daula Siddique

AbstractMultilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches. A level-shifted multilevel pulse width modulation scheme with a modified triangular carrier wave is implemented to produce a high-quality stepped output voltage waveform with low switching frequency. The proposed nine-level inverter’s effectiveness, driven by the recommended modulation technique, is experimentally verified under varying load conditions. The power loss and efficiency for the proposed nine-level inverter are thoroughly discussed with different loads.


2011 ◽  
Vol 130-134 ◽  
pp. 3392-3395 ◽  
Author(s):  
Gang Chen ◽  
Peng Wu ◽  
Song Bai ◽  
Zhe Yang Li ◽  
Yun Li ◽  
...  

. Silicon carbide (SiC) SITs were fabricated using home-grown epi structures. The gate is a recessed gate - bottom contact (RG - B). We designed that the mesa space 2.7μm and the gate channel is 1.2μm. One cell has 400 source fingers and each source finger width is 100μm. 1mm SiC SIT yielded a current density of 123mA/mm of drain current at a drain voltage of 20V. A maximum current density of 150 mA/mm was achieved with Vd=40V. The device blocking voltage with a gate bias of-16 V was 200 V. Packaged 24-cm devices were evaluated using amplifier circuits designed for class AB operations. A total power output in excess of 213 W was obtained with a power density of 8.5 W/cm and gain of 8.5 dB at 500 MHz under pulse operation.


2013 ◽  
Vol 740-742 ◽  
pp. 958-961 ◽  
Author(s):  
Shuji Katakami ◽  
Hiroyuki Fujisawa ◽  
Kensuke Takenaka ◽  
Hitoshi Ishimori ◽  
Shinji Takasu ◽  
...  

We fabricated and characterized an ultrahigh voltage (>10kV) p-channel silicon carbide insulated gate bipolar transistor (SiC-IGBT) with high channel mobility. Higher field-effect channel mobility of 13.5 cm2/Vs was achieved by the combination of adopting an n-type base layer with a retrograde doping profile and additional wet re-oxidation annealing (wet-ROA) at 1100°C in the gate oxidation process. The on-state characteristics of the p-channel SiC-IGBT at 200°C showed the low differential specific on-resistance of 24 mΩcm2 at VG = -20 V. The forward blocking voltage of the p-channel SiC-IGBT at 25°C was 10.2 kV a the leakage current density of 1.0 μA/cm2.


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