A Simple Method of Transistor-Level SPICE-Models Parameters Fitting of Integrated Circuits in a Temperature Range

2021 ◽  
Vol 26 (6) ◽  
pp. 547-553
Author(s):  
S.V. Shumarin ◽  
◽  
A.M. Bogachev ◽  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Fitting ◽  
Circuit Model ◽  
The Self ◽  
Ring Oscillator ◽  
Simple Method ◽  
Correlation Relationship ◽  
Temperature Range ◽  
Before And After

Today, both macromodels and transistor-level models of semiconductor integrated circuits are available. However, most models don’t take into account the influence of destabilizing effects. Thus, the tasks of developing new models and fitting the parameters of existing ones are very relevant. In this work, the authors introduced an assumption about the existence of a correlation relationship between all the parameters of integrated circuits’ transistor-level models and offered a way to fit these parameters. The experience of fitting the model’s parameters of the integrated circuit 1564LE1 EP was presented. To simplify this task, all parameters were altered by the same relative deviation. To check the assumption made, the authors carried out full-scale experiment, in which the frequency of the self-oscillation of the ring oscillator based on the 1564LE1 EP was measured in the temperature range. The simulation of the ring oscillator has been made using a SPICE-simulator. The dependences of the self-oscillation frequency on temperature, obtained as a result of simulation and as a result of experiment, were compared before and after fitting the parameters of the integrated circuit model. Also, the waveforms of the ring oscillator based on the original and fitted model were compared. The analysis of the obtained dependences of the frequency of oscillations, the signal shape before and after the model fitting, the link to the text of the fitted model has been provided. The results obtained show the possibility of using the introduced assumption to fit the parameters of the transistor-level integrated circuit model.

Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 15 (4) ◽  
pp. 163-170 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
And Control

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Characterization of 6H-SiC JFET Integrated Circuits over a Broad Temperature Range from -150 °C to +500 °C

2010 ◽  
Vol 645-648 ◽  
pp. 1135-1138 ◽  
Author(s):  
Philip G. Neudeck ◽  
Michael J. Krasowski ◽  
Liang Yu Chen ◽  
Norman F. Prokop
Keyword(s):  
Integrated Circuits ◽  
Logic Gate ◽  
Logic Gates ◽  
Ring Oscillator ◽  
Broad Temperature Range ◽  
Stable Operation ◽  
Cold Temperatures ◽  
Temperature Range ◽  
Circuit Input

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 °C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 °C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 °C to +500 °C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

scholarly journals Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

2018 ◽  
Vol 8 (8) ◽  
pp. 1331 ◽  
Author(s):  
Yasunori Takeda ◽  
Tomohito Sekine ◽  
Rei Shiwaku ◽  
Tomohide Murase ◽  
Hiroyuki Matsui ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Driving Voltage ◽  
Organic Thin Film ◽  
Voltage Range ◽  
Type D ◽  
Polymer Semiconductor ◽  
P Type

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000071-000078 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
One Year

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

scholarly journals Application of TIVA in Design Debug

2000 ◽  
Author(s):  
Siva Kolachina ◽  
Bill Taylor ◽  
Kendall Scott Wills ◽  
Edward I. Cole
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Ring Oscillator ◽  
Induced Voltage ◽  
Thermally Induced ◽  
Isolation Techniques ◽  
Limited Success ◽  
Focussed Ion Beam ◽  
Design Debugging

Abstract Thermally-Induced Voltage Alteration (TIVA) is a relatively new technique for locating electrical defects in integrated circuits [1,2]. This paper describes a novel application of TIVA, to locate design anomalies. A newly designed integrated circuit with high and inconsistent Quiescent Power Supply Current (IDDQ) was initially diagnosed with limited success using various failsite isolation techniques. The TIVA technique was successful in accurately locating design anomalies. Results from TIVA identified a spurious ring oscillator in the design. Design modifications carried out using a focussed ion beam (FIB), verified the accuracy of the results from TIVA. This study clearly extends the use of TIVA beyond that of locating electrical defects and anomalies into the realm of design debugging.

The Precipitation of Si in AlCuSi Thin Films

1973 ◽  
Vol 31 ◽  
pp. 34-35 ◽  
Author(s):  
R. M. Anderson
Keyword(s):  
Electron Microscopy ◽  
Thin Films ◽  
Heat Treatment ◽  
Solid Solution ◽  
Integrated Circuit ◽  
Copper Film ◽  
Solution Concentration ◽  
X Ray ◽  
Silicon Thin Films ◽  
Before And After

Aluminum-copper-silicon thin films have been considered as an interconnection metallurgy for integrated circuit applications. Various schemes have been proposed to incorporate small percent-ages of silicon into films that typically contain two to five percent copper. We undertook a study of the total effect of silicon on the aluminum copper film as revealed by transmission electron microscopy, scanning electron microscopy, x-ray diffraction and ion microprobe techniques as a function of the various deposition methods.X-ray investigations noted a change in solid solution concentration as a function of Si content before and after heat-treatment. The amount of solid solution in the Al increased with heat-treatment for films with ≥2% silicon and decreased for films <2% silicon.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Nanofabricated SiO2-Si-SiO2 Resonant Tunneling Diodes

2000 ◽  
Vol 631 ◽  
Author(s):  
J. G. Fleming ◽  
E. Chow ◽  
S.-Y. Lin
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Resonant Tunneling ◽  
Resonant Tunneling Diodes ◽  
Resonance Tunneling ◽  
Tunneling Diodes

ABSTRACTResonance Tunneling Diodes (RTDs) are devices that can demonstrate very highspeed operation. Typically they have been fabricated using epitaxial techniques and materials not consistent with standard commercial integrated circuits. We report here the first demonstration of SiO2-Si-SiO2 RTDs. These new structures were fabricated using novel combinations of silicon integrated circuit processes.

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