Laser Beam Based ESD Defect Localization in ICs

2002 ◽  
Author(s):  
Félix Beaudoin ◽  
Philippe Perdu ◽  
Romain Desplats ◽  
Emmanuel Doche ◽  
Alain Wislez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Low Voltage ◽  
Crystalline Silicon ◽  
Physical Analysis ◽  
Molten Silicon ◽  
Laser Stimulation ◽  
Current Consumption ◽  
Defect Localization ◽  
Stimulation Technique

Abstract The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.

scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Laser Stimulation Applied to Dynamic IC Diagnostics

2003 ◽  
Author(s):  
Félix Beaudoin ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
Abdellatif Firiti ◽  
Gerald Haller ◽  
...  
Keyword(s):  
Laser Beam ◽  
Near Infrared ◽  
Test Pattern ◽  
Infrared Laser ◽  
Continuous Laser ◽  
Laser Stimulation ◽  
Defect Localization ◽  
Resistive Defects

Abstract Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

Linewidth measurement using the low voltage SEM

1986 ◽  
Vol 44 ◽  
pp. 652-653
Author(s):  
M.G. Rosenfield
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Secondary Electron ◽  
Low Voltage ◽  
Fabrication Process ◽  
Critical Dimensions ◽  
Linewidth Measurement ◽  
Threshold Technique ◽  
Scanning Electron

Minimum feature sizes in experimental integrated circuits are approaching 0.5 μm and below. During the fabrication process it is usually necessary to be able to non-destructively measure the critical dimensions in resist and after the various process steps. This can be accomplished using the low voltage SEM. Submicron linewidth measurement is typically done by manually measuring the SEM micrographs. Since it is desirable to make as many measurements as possible in the shortest period of time, it is important that this technique be automated.Linewidth measurement using the scanning electron microscope is not well understood. The basic intent is to measure the size of a structure from the secondary electron signal generated by that structure. Thus, it is important to understand how the actual dimension of the line being measured relates to the secondary electron signal. Since different features generate different signals, the same method of relating linewidth to signal cannot be used. For example, the peak to peak method may be used to accurately measure the linewidth of an isolated resist line; but, a threshold technique may be required for an isolated space in resist.

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

Laser Failure Isolation Techniques Demonstrated On Test Structures

2008 ◽  
Author(s):  
Frank S. Arnold
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Case Studies ◽  
Induced Resistance ◽  
Simple Test ◽  
Resistance Change ◽  
Cross Sectional ◽  
Beam Focusing ◽  
Isolation Techniques ◽  
Heating Effects

Abstract To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.

Test Circuit Conditioning for Soft Defect Localization

2014 ◽  
Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich
Keyword(s):  
Laser Beam ◽  
Failure Analysis ◽  
Signal Frequency ◽  
Dynamic Failure ◽  
The Third ◽  
Analysis Technique ◽  
Test Circuit ◽  
Defect Localization ◽  
Manual Input ◽  
Fast Dynamic

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

Thermal Laser Stimulation Technique for AlGaN/GaN HEMT Technologies Improvement

2013 ◽  
Author(s):  
Dominique Carisetti ◽  
Nicolas Sarazin ◽  
Nathalie Labat ◽  
Nathalie Malbert ◽  
Arnaud Curutchet ◽  
...  
Keyword(s):  
Surface States ◽  
Leakage Currents ◽  
Laser Stimulation ◽  
Long Term Stability ◽  
Field Plate ◽  
Gan Hemt ◽  
Die Surface ◽  
Scan Speed ◽  
Stimulation Technique

Abstract To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

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