Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) Localization of 32nm SOI SRAM Array Failure

2009 ◽  
Author(s):  
Terence Kane ◽  
Michael P. Tenney
Keyword(s):  
Silicon On Insulator ◽  
Memory Devices ◽  
Access Memory ◽  
Metal Gate ◽  
Soi Mosfet ◽  
Scanning Capacitance Microscopy ◽  
High K ◽  
Capacitance Voltage

Abstract The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of FEOL defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET and SOI embedded dynamic ramdon access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy have also been highlighted [2]. This paper is intended to describe the advantages of NCVS to localize defects in specific MOSFET devices at CA level as well as to identify resistive BEOL via interconnections and FEOL defective high k metal gate structures without the attendant time consuming delayering steps employed with classical SCM methods. Localization of a FEOL defect in a discrete 32nm SOI MOSFET device in SRAM array causing a vertical pair cell failure signature will be discussed.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Improved high-temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

2010 ◽  
Vol 87 (5-8) ◽  
pp. 1629-1633 ◽  
Author(s):  
J. Paul ◽  
V. Beyer ◽  
M. Czernohorsky ◽  
M.F. Beug ◽  
K. Biedermann ◽  
...  
Keyword(s):  
High Temperature ◽  
Memory Devices ◽  
Gate Stacks ◽  
Metal Gate ◽  
High K

Wafer Level Atomic Force Probing

2010 ◽  
Author(s):  
Terence Kane ◽  
Sweta Pendyala ◽  
Michael P. Tenney
Keyword(s):  
Silicon On Insulator ◽  
Wafer Level ◽  
Access Memory ◽  
Laboratory Practice ◽  
Deep Trench ◽  
Atomic Force ◽  
Capacitance Voltage ◽  
First Time ◽  
Process Level ◽  
Insight Into

Abstract The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy has also been highlighted [1,2,3,4,5,6]. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300mm wafers at the post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool incorporates enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32nm, 28nm, and 20nm node technologies.

Ultra Thin Body Silicon-On-Insulator (UTB SOI) MOSFET with Metal Gate Work-function Engineering for sub-70 nm Technology Node

2002 ◽  
Author(s):  
Daewon Ha ◽  
Pushkar Ranade ◽  
Yang-Kyu Choi ◽  
Jeong-Soo Lee ◽  
Tsu-Jae King ◽  
...  
Keyword(s):  
Work Function ◽  
Silicon On Insulator ◽  
Thin Body ◽  
Metal Gate ◽  
Soi Mosfet ◽  
Technology Node ◽  
Utb Soi Mosfet ◽  
Gate Work Function

Performance Improvement of Pi-gate SOI MOSFET Transistor using High-k Dielectric with Metal Gate

2015 ◽  
Vol 62 (3) ◽  
pp. 331-338 ◽  
Author(s):  
Fatima Zohra Rahou ◽  
A. Guen Bouazza ◽  
B. Bouazza
Keyword(s):  
Performance Improvement ◽  
Metal Gate ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric

scholarly journals Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 1638-1642
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Structural Aspect ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Thin Body ◽  
Metal Gate ◽  
Short Channel ◽  
Soi Mosfet ◽  
Utb Soi Mosfet

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FB08 ◽  
Author(s):  
Eugenio Dentoni Litta ◽  
Romain Ritzenthaler ◽  
Tom Schram ◽  
Alessio Spessot ◽  
Barry O’Sullivan ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Metal Gate ◽  
High K

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FB10
Author(s):  
Yuichiro Ishii ◽  
Miki Tanaka ◽  
Makoto Yabuuchi ◽  
Yohei Sawada ◽  
Shinji Tanaka ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Cmos Technology ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Metal Gate ◽  
High K ◽  
28 Nm
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