Challenges for Parametric Analysis of the Solar Cells Using Failure Analysis Technique Developed for the Microelectronics

Author(s):  
M. Boostandoost ◽  
X. Ycaza ◽  
R. Leihkauf ◽  
U. Kerst ◽  
C. Boit

Abstract In this study, the challenges to transfer the microelectronics failure analysis techniques to the photovoltaic industry have been discussed. The main focus of this study was the PHEMOS as a tool with strong technological research capacity developed for microelectronics failure analysis, and OBIC (Optical Beam Induced Current) as a non-destructive technique for detecting and localizing various defects in semiconductor devices. This failure analysis tool was a high resolution optical infrared photon emission microscope used mainly in microelectronics for qualitative analysis and localization of semiconductor defects. Such failure analysis equipment was designed to meet requirements for modern microelectronic devices. Characterization of current photovoltaic device often requires quantitative analysis and should provide information about the electrical and material properties of the solar cell. Therefore, in addition to the demand for further data processing of the obtained results we had to study the corresponding operating regime of solar cells to allow for a correct interpretation of measurement results. In this paper, some of the related problems we faced during this study, e.g. large amount of data processing, the spatial misalignment of the images obtained as EL (Electroluminescence) and IR-LBIC (Infrared Light Beam Induced Current), the implemented laser wavelength, its profile and power density for IR-LBIC measurement. These topics have been discussed in detailed to facilitate a reliable transfer of these techniques from microelectronics to the photovoltaic world.

Author(s):  
M. Boostandoost ◽  
A. Glowacki ◽  
O. Bakaeva ◽  
U. Kerst ◽  
C. Boit

Abstract In this paper, IR-LBIC (Infrared Light Beam Induced Current) is applied using the laser wavelength of 1064 nm in order to analyze polycrystalline thin-film solar cells. The spatially high-resolved map of the short circuit current (~3 µm) has been obtained by performing the IR-LBIC measurement. The results of the measurement showed higher signal response from the grain boundary compared to that from the grain interior. This difference has been explained by the light trapping effect due to the trench-shaped grain boundary profile, which is possibly accompanied by two stage excitation effects via electronic grain boundary states. It has been additionally investigated, whether LBIC measurement could be used to extract local illuminated cell characteristics. However, since the dark current, which has a decisive influence on the solar cell characteristic, is flowing in the entire cell area, this is not possible. A circuit network simulation demonstrates that LBIC cannot be used for extraction of the local open circuit voltage, and the short circuit current is the only parameter that can be locally defined and therefore clearly observed.


Author(s):  
Jim Colvin

Abstract Photovoltaic devices (PV) or more commonly “solar cells” are analyzed using LBIC/LBIV (Light Beam Induced Current/Voltage) PL (Photoluminescence) and EL (Electroluminescence) as well as INSB thermal Methods. This paper will show the advantages and pitfalls of the techniques as well as a novel way to perform EL imaging without a dark box and thermal imaging through glass panels.


Author(s):  
C.Q. Chen ◽  
Z.H. Mai ◽  
G.B. Ang ◽  
B.H. Liu ◽  
P.T. Ng ◽  
...  

Abstract As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.


Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.


Author(s):  
K. Sanchez ◽  
G. Bascoul ◽  
F. Infante ◽  
N. Courjault ◽  
T. Nakamura

Abstract Magnetic field imaging is a well-known technique which gives the possibility to study the internal activity of electronic components in a contactless and non-invasive way. Additional data processing can convert the magnetic field image into a current path and give the possibility to identify current flow anomalies in electronic devices. This technique can be applied at board level or device level and is particularly suitable for the failure analysis of complex packages (stacked device & 3D packaging). This approach can be combined with thermal imaging, X-ray observation and other failure analysis tool. This paper will present two different techniques which give the possibility to measure the magnetic field in two dimensions over an active device. Same device and same level of current is used for the two techniques to give the possibility to compare the performance.


Author(s):  
Sarven Ipek ◽  
David Grosjean

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.


Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.


Author(s):  
Steve Ferrier ◽  
Kevin D. Martin ◽  
Donald Schulte

Abstract Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.


Author(s):  
Charles Zhang ◽  
Matt Thayer ◽  
Lowell Herlinger ◽  
Greg Dabney ◽  
Manuel Gonzalez

Abstract A number of backside analysis techniques rely on the successful use of optical beams in performing backside fault isolation. In this paper, the authors have investigated the influence of the 1340 nm and 1064 nm laser wavelength on advanced CMOS transistor performance.


Author(s):  
Mehrdad Mahanpour ◽  
Andy Gray ◽  
Jose Hulog ◽  
Pat Chang

Abstract C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.


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