Practical Dynamic Laser Stimulation Techniques for Complex Analog and Mixed Signal IC Failure Analysis

2017 ◽  
Author(s):  
Jeffrey Javier ◽  
Taylor Hurdle ◽  
Sammie Fernandez ◽  
Kari Van Vliet
Keyword(s):  
Failure Modes ◽  
Fault Isolation ◽  
Automatic Test Equipment ◽  
Temperature Dependent ◽  
Mixed Signal ◽  
Laser Stimulation ◽  
Isolation Techniques ◽  
Defect Sites ◽  
Dependent Failure ◽  
Development And Evolution

Abstract The increasing electrical design and physical complexity of semiconductor devices, especially in the analog and mixed signal (AMS) applications, directly influences the development and evolution of fault isolation techniques. One of these techniques is Dynamic Laser Stimulation (DLS) which is widely used in the industry for effective identification of subtle failure mechanisms and soft defects especially for AC signal-related failures [1, 2]. However, for analysis of some complex AMS IC failure modes, the tool’s standard setup may not always be compatible with the biasing requirements of the device. For example, the setup would typically require expensive and intricate test systems (i.e. Automatic test equipment (ATE), SCAN tester, etc.) to be interfaced with the DLS tool for the analysis to be feasible and successful [3, 4]. This paper presents simple and practical techniques to implement DLS without the need for an expensive test support system. These techniques were applied in three different FA cases involving AMS ICs with complex and temperature-dependent failure modes. The results of subsequent analysis indicated success in isolating the exact defect sites.

Tester-Driven Dynamic Laser Stimulation for Hard Functional Failure

2010 ◽  
Author(s):  
S.H. Goh ◽  
Y.H. Chan ◽  
F. Zheng ◽  
H. Tan ◽  
J.W. Ting ◽  
...  
Keyword(s):  
Laser Beam ◽  
Signal To Noise Ratio ◽  
Fault Isolation ◽  
Signal To Noise ◽  
Test Program ◽  
Functional Failure ◽  
Laser Stimulation ◽  
Automated Test Equipment ◽  
Isolation Techniques ◽  
Dynamic Techniques

Abstract Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniques are proven effective for localizing soft failures. In this paper, we demonstrate the feasibility of using such dynamic techniques for functional hard failures and design debug applications. We illustrate experimentally the significance of achieving sufficient signal to noise ratio (SNR) before such applications can be realized effectively, due to the large irregular noise that couples through as the functional pattern is run. We adopted a combination of hardware noise reduction and test program modification to overcome this challenge.

Combining Electron Beam Methods, EBIC and EBAC, with Traditional Approaches for Highly Effective Fault Isolation

2017 ◽  
Author(s):  
Ryan Fredrickson ◽  
Tim Kuebrich ◽  
Andrew Le ◽  
Derek Snider ◽  
Lucas Winiarski
Keyword(s):  
Electron Beam ◽  
Liquid Crystal ◽  
Local Heating ◽  
Interesting Case ◽  
Fault Isolation ◽  
Resistance Change ◽  
Cross Sectional ◽  
Defect Site ◽  
Isolation Techniques ◽  
Defect Sites

Abstract Fault isolation is an important initial component of the failure analysis investigation as it provides the first indicator of the defect physical location. The most broadly familiar fault isolation techniques include photoemission microscopy (PEM), optical beam induced resistance change (OBIRCH) and liquid crystal analysis (LCA). Each of these techniques has their own strengths but also drawbacks which can impede the analysis by either not providing a well isolated defect location or causing damage to the defect region. For some types of defects, photoemission and liquid crystal analysis may create local heating of the device which can distort the defect and mask the root cause of the failure. These techniques also rely on optical microscopy which has low resolution compared to the feature size of current technologies. In addition, each technique may not highlight the defect site itself; only pointing the analyst to the defective circuit within the sample. Electron Beam Induced Current (EBIC) and Electron Beam Absorbed Current (EBAC) microscopy provides solutions to these complications. In this paper we describe some very effective approaches by using these beam-based techniques in conjunction with traditional methods. As introduction, we have provided some interesting case studies whereby EBIC/EBAC have been used in conjunction with FIB circuit edits and scan diagnostic results to narrow the defect search areas. We focus the paper on some less common applications of cross sectional EBIC/EBAC as well as utilizing an AC coupled configuration to activate more subtle defect sites. We conclude with two examples where AC coupled cross-sectional EBIC is needed to highlight the cause of the failure.

scholarly journals Fault Identification and Isolation in Dynamic Systems Using Multiple Models

2019 ◽  
Vol 11 (1) ◽  
Author(s):  
Olivia Maria Alves Coelho ◽  
Wlamir O. L. Vianna ◽  
Takashi Yoneyama
Keyword(s):  
Dynamic Systems ◽  
Computational Models ◽  
Failure Modes ◽  
Fault Isolation ◽  
Fault Detection And Isolation ◽  
Multiple Models ◽  
Multiple Faults ◽  
Industrial Systems ◽  
Isolation Techniques ◽  
And Performance

The demand for more reliability, safety and performance in industrial systems is rapidly increasing every day. The early detection of faults can avoid catastrophic events and the identification of the fault nature and severity can lead to the most appropriated and efficient maintenance task. Thus, an enhanced system diagnosis feature has the potential to increase safety and reduce the operational costs. In this context, fault detection and isolation techniques are used as the basis for building powerful decision making tools. This work's objective is to identify and isolate multiple faults in dynamic systems through signal processing. An approach based on a multiple-models architecture is considered whereas the plant output signals is compared with simulation data from a set of models representing the failure modes being analysed. The Autonomous Multiple Models (AMM) technique is chosen for further residue estimation and fault isolation. A case study using computational models representing an electro-mechanical system is carried out in order to validate the proposed method and evaluate its performance and limitations such as failure modes not mapped through the models and its capability to handle concurrent faults.

Thermally Assisted Photoemission for CMOS Device Analysis

1998 ◽  
Author(s):  
K. Symonds ◽  
J. Wilson
Keyword(s):  
Failure Modes ◽  
Impact Ionization ◽  
Light Emission ◽  
Fault Isolation ◽  
Dominant Factor ◽  
Limiting Factor ◽  
Light Emitting ◽  
Physical Mechanisms ◽  
Isolation Techniques ◽  
Cmos Vlsi

Abstract Enhancement of Existing Fault Isolation Techniques for CMOS VLSI Failure Analysis is important in keeping pace with device design and process technologies. Recently, we enhanced our photoemission microscopy capability by applying heat to the device during analysis1. This provided greater defect related light emission from nSRAM test structures and allowed identification of subtle failure modes not observable during room temperature inspection. In the present work, we investigate the theoretical dependencies of emission mechanisms and analyze experimental data to identify the dominant physical mechanisms involved with thermally assisted photoemission. We introduce a thermal factor to help quantify the effect from various light emitting structures. Experimentally, we find that emission mechanisms involving leaky and forward junctions are enhanced by temperature, and propose that the dominant factor for increased signal may be an increasing contribution from phonon absorption rather than phonon emission-based recombination. For emission mechanisms based on impact ionization; however, we find that the emission response is inversely proportional to temperature, and show that mobility degradation is the dominant limiting factor at higher temperatures.

Root Cause Analysis of High Input Offset Voltage in Mixed-Signal Design Through Nanoprobing and Cadence Simulation

2019 ◽  
Author(s):  
Zhenni Wan ◽  
Weikai Yin ◽  
Yining Zang ◽  
Madhukar Karigerasi ◽  
Saurabh Kulkarni ◽  
...  
Keyword(s):  
Failure Modes ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
The Body ◽  
Cause Analysis ◽  
Mixed Signal ◽  
Root Cause ◽  
Offset Voltage ◽  
Amplifier Gain ◽  
Mixed Signal Ic

Abstract Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

2018 ◽  
Author(s):  
Daechul Choi ◽  
Yoonseong Kim ◽  
Jongyun Kim ◽  
Han Kim
Keyword(s):  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Isolation Techniques ◽  
Super Conducting ◽  
Non Destructive

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

A Novel OBIRCH Fault Isolation Method to Locate the Leakage Failure Point

2008 ◽  
Author(s):  
Chi-Lin Huang ◽  
Yu Hsiang Shu
Keyword(s):  
Semiconductor Device ◽  
Fault Isolation ◽  
Resistance Change ◽  
Cross Sectional ◽  
Isolation Technique ◽  
Isolation Techniques ◽  
Atomic Force ◽  
Analysis Experiment ◽  
Failure Point ◽  
Leakage Failure

Abstract Conventional isolation techniques, such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (PEM) frequently fail to locate failure points when only applied to power pin of the semiconductor device. In this paper, a novel OBIRCH failure isolation technique is utilized to detect leakage failures. Different test conditions are presented to identify the differences in current when all input pins are pulled high in an OBIRCH system. In order to verify a failure point, it is necessary to perform electrical analysis of the suspected failure point in the failing sample. In general, Conductive Atomic Force Microscope (C-AFM) and a Nano-Prober is sufficient to provide the electrical data required for failure analysis. Experiment results, however, prove that this novel OBIRCH failure isolation technique is effective in locating the failure point, especially for leakage failures. The failure mechanism is illustrated using cross-sectional TEM.

Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation

2016 ◽  
Author(s):  
Ramya Yeluri ◽  
Ravishankar Thirugnanasambandam ◽  
Cameron Wagner ◽  
Jonathan Urtecho ◽  
Jan M. Neirynck
Keyword(s):  
Duty Cycle ◽  
Thermal Effects ◽  
Second Harmonic ◽  
Fault Isolation ◽  
Advanced Technology ◽  
Temperature Dependent ◽  
First Case ◽  
Improve Accuracy ◽  
Degradation Monitoring ◽  
Technology Nodes

Abstract Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

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