scholarly journals Analog Multiplier Based on Squarer Cells

2019 ◽  
pp. 350-354
Author(s):  
Reza Zarei ◽  
Moora Maali
Keyword(s):  
Supply Voltage ◽  
Current Mode ◽  
Low Power Consumption ◽  
Analog Multiplier ◽  
Body Effect ◽  
Weak Inversion ◽  
Inversion Region ◽  
Input Range ◽  
Low Supply Voltage ◽  
A Current

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

scholarly journals A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE

2015 ◽  
pp. 171-174
Author(s):  
MOHAMMAD HADI DANESH ◽  
SASAN NIKSERESHT ◽  
MAHYAR DEHDAST
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Input Range ◽  
Low Supply Voltage

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

scholarly journals A CMOS CURRENT-MODE LOW POWER RMS-TO-DC CONVERTER

2015 ◽  
pp. 210-214
Author(s):  
MOHAMMAD HADI DANESH ◽  
MAHYAR DEHDAST ◽  
ABDOLGHANI AREKHI ◽  
AMIN EMAMI FARD
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Input Range ◽  
Low Supply Voltage

In this paper a low-power current-mode RMS-to-DC converter is proposed. The converter includes two-quadrant squarer/divider and the first-order low-pass filter cell, both of them use MOS translinear loops. The RMS-to-DC converter has low power consumption (< 0.75μW), low supply voltage (0.8 V), wide input range (from 40 nA to 500 nA), low relative error (< 3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

A New Low Voltage Analog Circuit Model for Hodgkin–Huxley Neuron Employing FGMOS Transistors

2018 ◽  
Vol 27 (09) ◽  
pp. 1850141
Author(s):  
Ava Salmanpour ◽  
Ebrahim Farshidi ◽  
Karim Ansari Asl
Keyword(s):  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Circuit Model ◽  
Weak Inversion ◽  
Combined Action ◽  
Low Costs ◽  
Low Supply Voltage ◽  
Channel Currents

A low voltage analog VLSI circuit model for Hodgkin–Huxley (HH) neuron cell equations (HH neuron model) is presented. Floating gate MOSFET (FGMOS) transistors in weak inversion region have been used to model HH equations such as gating variables, [Formula: see text] and [Formula: see text] functions and combined action of [Formula: see text], [Formula: see text] and [Formula: see text]. The combination of [Formula: see text], [Formula: see text] and [Formula: see text] controls the Na[Formula: see text] and K[Formula: see text] channel currents. The superiorities of the proposed circuits are low supply voltage, low power consumption, less circuit complexity and as a result, low costs are compared to the previous works. The proposed circuit which uses 24 transistors is simulated in Hspice software using 0.18[Formula: see text] technology and consumes 119[Formula: see text][Formula: see text]W.

scholarly journals A New Translinear-Based Dual-Output Square-Rooting Circuit

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
Montree Kumngern ◽  
Kobchai Dejhan
Keyword(s):  
Temperature Stability ◽  
Current Mode ◽  
Input Current ◽  
Absolute Value ◽  
Current Mirrors ◽  
Input Range ◽  
Simulation Results ◽  
Simulator Program ◽  
Mode Technique ◽  
A Current

A new wide input range square-rooting circuit is presented. The proposed circuit consists of a dual translinear loop, an absolute value circuit, and current mirrors. A current-mode technique is used to provide wide input range with simple circuitry. The output signal of the proposed circuit is the current which is proportional to the square root of input current. The proposed square-rooting circuit was confirmed by using PSpice simulator program. The simulation results demonstrate that the proposed circuit provides the excellent temperature stability with wide input current range.

scholarly journals 1.5-V CMOS Current Multiplier/Divider

2018 ◽  
Vol 8 (3) ◽  
pp. 1478 ◽  
Author(s):  
Jetsdaporn Satansup ◽  
Worapong Tangsrirat
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Total Power ◽  
Total Power Consumption ◽  
Linearity Error ◽  
Low Supply Voltage ◽  
Circuit Technique

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented.  It is based on the use of a compact current quadratic cell able to operate at low supply voltage.  The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V.  Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

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