Pre-Applied Inter Chip Fill for 3D-IC Chip Joining

2015 ◽  
Author(s):  
Yasuhiro Kawase ◽  
Makoto Ikemoto ◽  
Masaya Sugiyama ◽  
Hidehiro Yamamoto ◽  
Hideki Kiritani
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Conductive Filler ◽  
3D Ic ◽  
Fine Pitch ◽  
Silica Filler ◽  
Conductive Fillers ◽  
Process Compatibility

Three dimensional integrated circuits (3D-IC) have been proposed for the purpose of low power and high performance in recent years. Pre-applied inter chip fill is required for fine pitch interconnections, large chips, and also thin chips. In addition to them, pre-applied joining process with high thermal conductive inter chip fill (HT-ICF) is strongly required for the cooling of 3D-IC. Some kinds of matrix resins and thermal conductive fillers were simulated and evaluated for pre-applied ICF. As a result, matrix and cure agent appeared to be important to both pre-applied ICF process compatibility and thermal conductivity, so that we’d selected epoxy type matrix based on controlling super molecular structure due to its mesogen unit. And not only matrix but also filler appeared to be the key to improve thermal conductivity for pre-applied ICF at the same time. The thermal conductivity of conventional silica filler was only 1W/mK, so that, taking into account of thermal conductivity, density and its stability, we’d selected aluminum oxide and boron nitride as thermal conductive filler and optimized HT-ICF for pre-applied process. After composite was mixed and cured, some physical properties were measured and thermal conductivity was 1.8W/mK, CTE was below 21ppm/K and Tg was 120°C. Furthermore, new high thermal conductive filler was also studied. We’d synthesized completely new spherical BN (diameter <5um) and applied it to HT-ICF and the thermal conductivity was almost two times higher than conventional BN. In this study, we confirmed ICF physical characteristics and its pre-applied joining for 3D-IC and void-less joining was also discussed.

High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000408-000413
Author(s):  
Y. Kawase ◽  
M. Ikemoto ◽  
M. Yamazaki ◽  
M. Sugiyama ◽  
H. Kiritani ◽  
...  
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Narrow Gap ◽  
Flux Agent ◽  
3D Ic ◽  
Conductive Materials ◽  
Highly Active ◽  
Fine Pitch ◽  
Joining Process ◽  
Active Flux

Three dimensional (3D) IC has been proposed for high performance and low power in recent years. Due to the narrow gap between stacked chips and fine pitch of bumps, new inter chip fill (ICF) which can be used for pre-applied ICF process is required. The heat generation of 3D-IC is higher than 2D, so that a high thermal conductive inter chip fill (HT-ICF) is simultaneously required to dissipate the heat from 3D-IC and for the purpose of pre-applied ICF and HT-ICF, highly active flux agent and thermal conductive materials such as filler and matrix have been called for at the same time. In this study, some kind of materials were prepared, synthesized and optimized for the HT-ICF, and we evaluated its characteristic and confirmed applicability to pre-applied joining for 3D-IC.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Pre-applied Inter Chip Fill for 3D-IC Joining

2014 ◽  
Vol 2014 (1) ◽  
pp. 000242-000246 ◽  
Author(s):  
Y. Kawase ◽  
M. Ikemoto ◽  
M. Sugiyama ◽  
H. Kiritani ◽  
F. Mizutani ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Three Dimensional ◽  
Physical Characteristics ◽  
Two Dimensional ◽  
3D Ic ◽  
Thermal Compression ◽  
Low Viscosity

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required. In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

Constructing Three-dimensional Nano-crystalline Diamond Network within Polymer Composites for Enhanced Thermal Conductivity

Nanoscale ◽  
2021 ◽  
Author(s):  
Shaoyang Xiong ◽  
Yue Qin ◽  
Linhong Li ◽  
Guoyong Yang ◽  
Maohua Li ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Polymer Composites ◽  
Thermal Performance ◽  
Thermal Transport ◽  
High Performance ◽  
Rapid Development ◽  
Electronic Devices ◽  
Three Dimensional ◽  
Nano Crystalline ◽  
Enhanced Thermal Conductivity

In order to meet the requirement of thermal performance with the rapid development of high-performance electronic devices, constructing a three-dimensional thermal transport skeleton is an effective method for enhancing thermal...

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications

2011 ◽  
Vol 2011 (1) ◽  
pp. 001028-001032
Author(s):  
Michael J. O’Reilly ◽  
Jeff Leal ◽  
Suzette K. Pangrle ◽  
Kenneth Vartanian
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Contact Printing ◽  
Wire Bond ◽  
Printing System ◽  
3D Printed ◽  
Working Distance ◽  
Aerosol Jet Deposition ◽  
Vertical Interconnect

Aerosol Jet deposition systems provide an evolutionary alternative to both wire bond and TSV technology. As part of the Vertical Interconnect Pillar (ViP™) process, the Aerosol Jet system prints high density three-dimensional (3D) interconnects enabling multi-function integrated circuits to be stacked and vertically interconnected in high performance System-in-Packages (SiP). The stacks can include two or more die, with a total height of ∼ 2 millimeters. The non-contact printing system has a working distance of several millimeters above the substrate allowing 3D interconnects to be printed with no Z-height adjustments. The Aerosol Jet printhead is configured with multiple nozzles and a closely coupled atomizer to achieve production throughput of greater than 19,000 interconnects per hour. The Aerosol Jet printer deposits silver fine particle ink to form connections on staggered die stacks. High aspect ratio interconnects, less than 30-microns wide and greater than 6-microns tall, are printed at sub 60-micron pitch. After isothermal sintering at 150° C to 200° C for 30 minutes, highly conductive interconnects near bulk resistivity are produced. Pre-production yields exceeding 80% have been realized. This paper will provide further details on the 3D printed interconnect process, current and planned production throughput levels, and process yield and device reliability status.

Three-Dimensional Graphite Filled Poly(Vinylidene Fluoride) Composites with Enhanced Strength and Thermal Conductivity

2020 ◽  
Vol 842 ◽  
pp. 63-68
Author(s):  
Xiao Zhang ◽  
Jian Zheng ◽  
Yong Qiang Du ◽  
Chun Ming Zhang
Keyword(s):  
Mechanical Properties ◽  
Thermal Conductivity ◽  
Energetic Materials ◽  
High Performance ◽  
Vinylidene Fluoride ◽  
3D Structure ◽  
Three Dimensional ◽  
3D Network ◽  
Poly Vinylidene Fluoride ◽  
Polymer Bonded Explosives

Three-dimensional (3D) network structure has been recognized as an efficient approach to enhance the mechanical and thermal conductive properties of polymeric composites. However, it has not been applied in energetic materials. In this work, a fluoropolymer based composite with vertically oriented and interconnected 3D graphite network was fabricated for polymer bonded explosives (PBXs). Here, the graphite and graphene oxide platelets were mixed, and self-assembled via rapid freezing and using crystallized ice as the template. The 3D structure was finally obtained by freezing-dry, and infiltrating with polymer. With the increasing of filler fraction and cooling rate, the thermal conductivity of the polymer composite was significantly improved to 2.15 W m-1 K-1 by 919% than that of pure polymer. Moreover, the mechanical properties, such as tensile strength and elastic modulus, were enhanced by 117% and 563%, respectively, when the highly ordered structure was embedded in the polymer. We attribute the increased thermal and mechanical properties to this 3D network, which is beneficial to the effective heat conduction and force transfer. This study supports a desirable way to fabricate the strong and thermal conductive fluoropolymer composites used for the high-performance polymer bonded explosives (PBXs).

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process

2005 ◽  
Vol 867 ◽  
Author(s):  
J. J. McMahon ◽  
F. Niklaus ◽  
R. J. Kumar ◽  
J. Yu ◽  
J.Q. Lu ◽  
...  
Keyword(s):  
High Performance ◽  
Removal Rate ◽  
Three Dimensional ◽  
Surface Damage ◽  
Wafer Level ◽  
Razor Blade ◽  
3D Ic ◽  
3D Technology ◽  
Process Step ◽  
Wide Range

AbstractWafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a viafirst 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-to-Cu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding.In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190°C to 250°C, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test.

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