scholarly journals Experimental and simulation results of a symmetrical pad to reduce a stray ground current in superconducting integrated circuits

2017 ◽  
Vol 871 ◽  
pp. 012067
Author(s):  
H Suzuki ◽  
T Ono ◽  
N Yoshikawa
Keyword(s):  
Integrated Circuits ◽  
Ground Current ◽  
Simulation Results

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Wear of a Tool in Double-Disk Lapping of Silicon Wafers

2010 ◽  
Author(s):  
Adam Barylski ◽  
Mariusz Deja
Keyword(s):  
Experimental Data ◽  
Integrated Circuits ◽  
Tool Wear ◽  
Silicon Wafers ◽  
Silicon Ingot ◽  
Proposed Model ◽  
Tool Wear Prediction ◽  
Simulation Results ◽  
High Degree ◽  
Kinematical Parameters

Silicon wafers are the most widely used substrates for fabricating integrated circuits. A sequence of processes is needed to turn a silicon ingot into silicon wafers. One of the processes is flattening by lapping or by grinding to achieve a high degree of flatness and parallelism of the wafer [1, 2, 3]. Lapping can effectively remove or reduce the waviness induced by preceding operations [2, 4]. The main aim of this paper is to compare the simulation results with lapping experimental data obtained from the Polish producer of silicon wafers, the company Cemat Silicon from Warsaw (www.cematsil.com). Proposed model is going to be implemented by this company for the tool wear prediction. Proposed model can be applied for lapping or grinding with single or double-disc lapping kinematics [5, 6, 7]. Geometrical and kinematical relations with the simulations are presented in the work. Generated results for given workpiece diameter and for different kinematical parameters are studied using models programmed in the Matlab environment.

scholarly journals Bitstream Photon Counting Chirped AM Lidar with a Dual Unipolar Signal

2020 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Integrated Circuits ◽  
Phase I ◽  
Signal To Noise Ratio ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Sinusoidal Signal ◽  
Oxide Semiconductor ◽  
Quadrature Phase ◽  
Simulation Results

This paper is a follow-up to three previous papers: the first introducing the new Bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with the unipolar Digital Logic Local Oscillator (DLLO) concept, the second introducing the improvement thereof using the bipolar DLLO, and the third introducing the improvement of digital In-phase and Quadrature-phase (I/Q) demodulation.In that previous work, the signal was a single unipolar chirped sinusoidal or square wave. This paper introduces a new bitstream PC-CAML transceiver architecture that combines two unipolar chirped signals, referred to as the dual unipolar signal, to form a single bipolar signal in the receiver. (patent pending) This bipolar signal is mixed with the bipolar DLLOs in the in-phase (I) digital mixing and quadrature-phase (Q) digital mixing channels for digital I/Q demodulation for improved signal-to-noise ratio (SNR) compared to that when using a single unipolar signal.The simulation results presented in this paper indicate an SNR improvement for the dual unipolar chirped sinusoidal signal bitstream PC-CAML compared to that of the unipolar chirped sinusoidal signal bitstream PC-CAML (both with bipolar DLLOs and digital I/Q demodulation) of from about 3 dB to about 6 dB for signals below the onset of receiver saturation, and an improvement for maximum achievable SNR of about 13 dB if the receiver is allowed to saturate.The bitstream PC-CAML with a dual unipolar signal and bipolar DLLOs with digital I/Q demodulation architecture discussed in this paper adds complexity to the transmitter and receiver compared to the architectures presented in the previous papers. Whether or not this additional complexity is worth the improved SNR will have to be decided as part of system trade studies for particular systems and their applications.However, the new architecture still retains the key advantages of the previous bitstream PC-CAML architectures since it still replaces bulky, power-hungry, and expensive wideband RF analog electronics in the receiver with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous standard PC-CAML systems.This paper introduces the dual unipolar signal and bipolar DLLOs with digital I/Q demodulation transceiver architecture for bitstream PC-CAML, and presents the initial SNR theory with comparisons to Monte Carlo simulation results.

scholarly journals EVALUATION OF INTEGRATED ANALOG RC FILTER STRUCTURES FOR MULTISTANDARD TRANSCEIVERS / INTEGRINIŲ ANALOGINIŲ RC FILTRŲ STRUKTŪRŲ DAUGIASTANDARČIAMS SIŲSTUVAMS-IMTUVAMS TYRIMAS

2016 ◽  
Vol 8 (3) ◽  
pp. 315-320
Author(s):  
Karolis Kiela ◽  
Aleksandr Mamajev ◽  
Romualdas Navickas
Keyword(s):  
Integrated Circuits ◽  
Low Noise ◽  
Filter Bandwidth ◽  
Output Noise ◽  
Low Pass ◽  
Simulation Results ◽  
Response Variation ◽  
Low Pass Filters ◽  
Filter Structures ◽  
Filter Frequency

Multistandard transceivers usually have high order low pass filters in their receiver chains. Different filter topologies may have various component variation tolerances and different output noise. In this work, three 6th order filter with different topologies are analyzed for use in multistandard transceivers. Filters are designed in 0.18 µm and 65 nm CMOS technologies and simu-lated using Cadence software. The results show, that the filter frequency response variation in integrated circuits does not de-pend on the filter topology. Simulation results also show that the Leapfrog filter topology has the smallest integrated output noise in the filter bandwidth and is most suited for low noise applications. Daugiaustandarčiuose siųstuvuose-imtuvuose naudojami aukštesnės eilės žemųjų dažnių filtrai. Skirtingos filtrų struktūros gali būti nevienodai jautrios jas sudarančių elementų nuokrypiams ir daryti skirtingą įtaką daugiastandarčių siųstuvų-imtuvų triukšmams. Darbe pateikti trijų šeštosios eilės skirtingų struktūrų aktyviųjų RC filtrų, skirtų daugiaustandarčiams siųstuvams-imtuvams, tyrimo rezultatai. Filtrų struktūros modeliuojamos naudojant 0,18 μm ir 65 nm KMOP integrinių grandynų gamybos technologijas ir Cadence Virtuoso programinę įrangą. Iš imitacijos rezultatų matyti, kad moderniose integrinių grandynų technologijose filtrų dažninių amplitudės charakteristikų (DACh) parametrų nuokrypis beveik nepriklauso nuo filtro struktūros. Tarp analizuotų filtrų struktūrų mažiausia praleidžiamųjų dažnių juostoje integruota išėjimo triukšmo vidutinė kvadratinė vertė gaunama naudojant šuolinių grįžtamųjų ryšių struktūros filtrus.

Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Zhenyu Tang ◽  
Xiaoyan Tang ◽  
Shi Pu ◽  
Yimeng Zhang ◽  
Hang Zhang ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Device Simulation ◽  
Reference Value ◽  
Common Source ◽  
Content Type ◽  
Spice Model ◽  
Temperature Application ◽  
Simulation Results

Purpose To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required. Design/methodology/approach In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated. Findings The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures. Originality/value This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

Hardware Trojan Horse Detection through Improved Switching of Dormant Nets

2021 ◽  
Vol 17 (3) ◽  
pp. 1-22
Author(s):  
Tapobrata Dhar ◽  
Surajit Kumar Roy ◽  
Chandan Giri
Keyword(s):  
Integrated Circuits ◽  
Manufacturing Process ◽  
Test Phase ◽  
Side Channel ◽  
Hardware Trojan ◽  
Side Channel Analysis ◽  
Area Overhead ◽  
Channel Analysis ◽  
Testability Measures ◽  
Simulation Results

Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.

An Active Capacitance Multiplier Based on Switched-Capacitor DC-DC Converter

2012 ◽  
Vol 263-266 ◽  
pp. 76-79
Author(s):  
Hui Kai Fu
Keyword(s):  
Integrated Circuits ◽  
Charge Pump ◽  
Switched Capacitor ◽  
Fully Integrated ◽  
Monolithic Integrated Circuits ◽  
Simulation Results ◽  
Output Characteristics ◽  
On Chip ◽  
Floating Capacitor ◽  
Capacitance Multiplier

A technique of replacing the floating capacitor by an active capacitance multiplier is proposed in this paper, in order to overcome the difficulty in fabrication of the large capacitors in monolithic integrated circuits. The simulation results show that the same output characteristics can be obtained from the new charge pump with a capacitor much smaller than that adopted in the normal charge pump products. Therefore, the new charge pump is much easier to be fabricated in fully integrated realizations with on-chip capacitor.

scholarly journals Performance Efficient Alu using Finfet

2019 ◽  
Vol 8 (4) ◽  
pp. 11449-11455
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Power Analysis ◽  
High Speed ◽  
Power Saving ◽  
Arithmetic Functions ◽  
Power Efficient ◽  
Logical Unit ◽  
Simulation Results ◽  
Logical Functions

According to the prophecy of Moore, the concentration of transistors in an integrated circuit doubles every two years. But this is limited by the technologies used in the fabrication of integrated circuits, as the systems are scaled down. FinFET technology aims to combat this challenge. The construction of power efficient high speed Arithmetic & Logical Unit (ALU) using FinFET technology is proposed in this paper. Proposed FinFET based ALU is designed with arithmetic functions like high speed addition, multiplication and logical functions such as AND and XOR. Simulation results of the proposed power efficient high speed FinFET ALU proves to be better with a power saving of 80.5%. FinFET has the advantage of providing low power without compromising on the Performance. The power analysis for ALU is done using CADENCE-VIRTUOSO, which is known for its accuracy.

CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs

2019 ◽  
Vol 29 (11) ◽  
pp. 2050144
Author(s):  
Tianming Ni ◽  
Yue Shu ◽  
Hao Chang ◽  
Lin Lu ◽  
Guangzhen Dai ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Cost Effective ◽  
Bonding Process ◽  
High Yield ◽  
Repair Rate ◽  
3D Ics ◽  
Simulation Results ◽  
Silicon Vias

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring increases the faulty TSVs (FTSV), i.e., the TSV defects tend to be clustered which significantly reduces the yield of three-dimensional integrated circuits (3D-ICs). To resolve the clustered TSV faults, router-based and ring-based redundant TSV (RTSV) architecture were proposed. However, the repair rate is low and the hardware overhead is high. In this paper, we propose a novel cross-cellular based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has higher repair rate as well as more cost-effective overhead, compared with router-based and ring-based methods.

Delay Incurred in Wireless Sensor Networks Using N-Policy M/M/1 Queuing Model and its Mitigation

2019 ◽  
Vol 8 (2) ◽  
pp. 40-52 ◽  
Author(s):  
Sanjeev Ghosh ◽  
Srija Unnikrishnan
Keyword(s):  
Wireless Sensor Networks ◽  
Wireless Sensor Network ◽  
Integrated Circuits ◽  
Sensor Node ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Queuing Model ◽  
Mean Waiting Time ◽  
Simulation Results ◽  
Theoretical Results

Technological advancements in low power integrated circuits and wireless communications have led to the feasibility of using a network of sensors to be used for the collection, processing, analysis, and distribution of important information, collected in a wide variety of environments. Sensor nodes in a wireless sensor network face the issue of scarcity of power and therefore, optimal use of available power is of prime importance. The authors study and analyze a technique that aims to reduce the consumption of power. In this technique the radio of the sensor node is switched on only when the number of packets in a queue exceeds a certain threshold; this however introduces delay in the processing of the packets. The authors analyze the performance of this system with respect to the power consumption and mean waiting time and suggest a way to mitigate the delay. The simulations performed show that the simulation results are close to the theoretical results thus indicating the validity of the technique studied.

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