scholarly journals On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

Electronics ◽  
2021 ◽  
Vol 10 (24) ◽  
pp. 3148
Author(s):  
Martín Alejandro Valencia-Ponce ◽  
Esteban Tlelo-Cuautle ◽  
Luis Gerardo de la Fraga
Keyword(s):  
Fractional Order ◽  
Optimization Algorithms ◽  
Cmos Technology ◽  
Operational Amplifiers ◽  
Chaotic Oscillator ◽  
Silicon Area ◽  
Cmos Integrated Circuit ◽  
Multi Objective ◽  
Trade Offs ◽  
Fractional Order Integrator

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

scholarly journals PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 252 ◽  
Author(s):  
Victor Carbajal-Gomez ◽  
Esteban Tlelo-Cuautle ◽  
Carlos Sanchez-Lopez ◽  
Francisco Fernandez-Fernandez
Keyword(s):  
Integrated Circuit ◽  
Secure Communication ◽  
Piecewise Linear ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Chaotic Attractors ◽  
Chaotic Oscillator ◽  
Maximum Lyapunov Exponent ◽  
Chaotic Oscillators ◽  
Cmos Integrated Circuit

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

scholarly journals CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators

2021 ◽  
Vol 5 (3) ◽  
pp. 122
Author(s):  
Martín Alejandro Valencia-Ponce ◽  
Perla Rubí Castañeda-Aviña ◽  
Esteban Tlelo-Cuautle ◽  
Victor Hugo Carbajal-Gómez ◽  
Victor Rodolfo González-Díaz ◽  
...  
Keyword(s):  
Fractional Order ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Chaotic Oscillators ◽  
Operational Transconductance Amplifiers ◽  
Fractional Order Integrator ◽  
The Mathematical Model ◽  
Good Agreement

Fractional-order chaotic oscillators (FOCOs) have shown more complexity than integer-order chaotic ones. However, the majority of electronic implementations were performed using embedded systems; compared to analog implementations, they require huge hardware resources to approximate the solution of the fractional-order derivatives. In this manner, we propose the design of FOCOs using fractional-order integrators based on operational transconductance amplifiers (OTAs). The case study shows the implementation of FOCOs by cascading first-order OTA-based filters designed with complementary metal-oxide-semiconductor (CMOS) technology. The OTAs have programmable transconductance, and the robustness of the fractional-order integrator is verified by performing process, voltage and temperature variations as well as Monte Carlo analyses for a CMOS technology of 180 nm from the United Microelectronics Corporation. Finally, it is highlighted that post-layout simulations are in good agreement with the simulations of the mathematical model of the FOCO.

MOSFET-ONLY TWO-STAGE OPERATIONAL AMPLIFIERS WITH MILLER COMPENSATION: DESIGN AND FABRICATION IN NANO-SCALE CMOS

2013 ◽  
Vol 22 (08) ◽  
pp. 1350065 ◽  
Author(s):  
HAMED AMINZADEH
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Operational Amplifiers ◽  
Mos Capacitors ◽  
Silicon Area ◽  
Miller Compensation ◽  
Nano Scale ◽  
Metal Insulator Metal ◽  
Alternative Choice ◽  
Mim Capacitors

Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio.

scholarly journals Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

2020 ◽  
Author(s):  
Sven Gesper ◽  
Moritz Weißbrich ◽  
Tobias Stuckenberg ◽  
Pekka Jääskeläinen ◽  
Holger Blume ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Cmos Technology ◽  
Control Flow ◽  
Processor Architecture ◽  
Embedded Processor ◽  
Silicon Area ◽  
Trade Offs ◽  
Advanced Control ◽  
Flow Mechanisms ◽  
Technology Nodes

AbstractMicrocontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

scholarly journals Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 121
Author(s):  
Mattia Cicalini ◽  
Massimo Piotto ◽  
Paolo Bruschi ◽  
Michele Dei
Keyword(s):  
Cmos Technology ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Trade Offs ◽  
Monitoring Applications ◽  
Linearity Error ◽  
Energy Constrained

The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/∘C in the −40 ∘C, +125 ∘C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.

scholarly journals A Comparison of Genetic Representations and Initialisation Methods for the Multi-objective Shortest Path Problem on Multigraphs

2021 ◽  
Vol 2 (3) ◽  
Author(s):  
Lilla Beke ◽  
Michal Weiszer ◽  
Jun Chen
Keyword(s):  
Shortest Path ◽  
Time Budget ◽  
Exact Algorithm ◽  
Simple Graph ◽  
Shortest Path Problem ◽  
Future Application ◽  
Multi Objective ◽  
Trade Offs ◽  
Conflicting Objectives ◽  
Problem Instances

AbstractThis paper compares different solution approaches for the multi-objective shortest path problem (MSPP) on multigraphs. Multigraphs as a modelling tool are able to capture different available trade-offs between objectives for a given section of a route. For this reason, they are increasingly popular in modelling transportation problems with multiple conflicting objectives (e.g., travel time and fuel consumption), such as time-dependent vehicle routing, multi-modal transportation planning, energy-efficient driving, and airport operations. The multigraph MSPP is more complex than the NP-hard simple graph MSPP. Therefore, approximate solution methods are often needed to find a good approximation of the true Pareto front in a given time budget. Evolutionary algorithms have been successfully applied for the simple graph MSPP. However, there has been limited investigation of their applications to the multigraph MSPP. Here, we extend the most popular genetic representations to the multigraph case and compare the achieved solution qualities. Two heuristic initialisation methods are also considered to improve the convergence properties of the algorithms. The comparison is based on a diverse set of problem instances, including both bi-objective and triple objective problems. We found that the metaheuristic approach with heuristic initialisation provides good solutions in shorter running times compared to an exact algorithm. The representations were all found to be competitive. The results are encouraging for future application to the time-constrained multigraph MSPP.

Bilateral Photoplethysmography Analysis for Peripheral Arterial Stenosis Screening With a Fractional-Order Integrator and Info-Gap Decision-Making

2016 ◽  
Vol 16 (8) ◽  
pp. 2691-2700 ◽  
Author(s):  
Jian-Xing Wu ◽  
Chien-Ming Li ◽  
Yueh-Ren Ho ◽  
Ming-Jui Wu ◽  
Ping-Tzan Huang ◽  
...  
Keyword(s):  
Decision Making ◽  
Fractional Order ◽  
Arterial Stenosis ◽  
Fractional Order Integrator ◽  
Peripheral Arterial

scholarly journals Comparative Study of Discrete Component Realizations of Fractional-Order Capacitor and Inductor Active Emulators

2018 ◽  
Vol 27 (11) ◽  
pp. 1850170 ◽  
Author(s):  
Georgia Tsirimokou ◽  
Aslihan Kartci ◽  
Jaroslav Koton ◽  
Norbert Herencsar ◽  
Costas Psychalinos
Keyword(s):  
Comparative Study ◽  
Fractional Order ◽  
High Performance ◽  
Continued Fraction ◽  
Transfer Functions ◽  
Operational Amplifiers ◽  
Current Conveyors ◽  
Continued Fraction Expansion ◽  
Current Feedback ◽  
Discrete Component

Due to the absence of commercially available fractional-order capacitors and inductors, their implementation can be performed using fractional-order differentiators and integrators, respectively, combined with a voltage-to-current conversion stage. The transfer function of fractional-order differentiators and integrators can be approximated through the utilization of appropriate integer-order transfer functions. In order to achieve that, the Continued Fraction Expansion as well as the Oustaloup’s approximations can be utilized. The accuracy, in terms of magnitude and phase response, of transfer functions of differentiators/integrators derived through the employment of the aforementioned approximations, is very important factor for achieving high performance approximation of the fractional-order elements. A comparative study of the accuracy offered by the Continued Fraction Expansion and the Oustaloup’s approximation is performed in this paper. As a next step, the corresponding implementations of the emulators of the fractional-order elements, derived using fundamental active cells such as operational amplifiers, operational transconductance amplifiers, current conveyors, and current feedback operational amplifiers realized in commercially available discrete-component IC form, are compared in terms of the most important performance characteristics. The most suitable of them are further compared using the OrCAD PSpice software.

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